================================================================================
DATE : Mar 22,2023
TO : Multi-Core Intel(R) Xeon(R) Processor-Based Server Platform customers
SUBJECT : BIOS Release notes
================================================================================
                           LEGAL INFORMATION
================================================================================

Information in this document is provided in connection with Intel Products
and for the purpose of supporting Intel developed server boards and systems.
No license, express or implied, by estoppel or otherwise, to any intellectual 
property rights is granted by this document. Except as provided in Intel's 
Terms and Conditions of Sale for such products, Intel assumes no liability 
whatsoever, and Intel disclaims any express or implied warranty, relating to 
sale and/or use of Intel products including liability or warranties relating 
to fitness for a particular purpose, merchantability, or infringement of any 
patent, copyright or other intellectual property right. Intel Corporation 
may have patents or pending patent applications, trademarks, copyrights, or
other intellectual property rights that relate to the presented subject matter.
The furnishing of documents and other materials and information does not 
provide any license, express or implied, by estoppel or otherwise, to any such
patents, trademarks, copyrights, or other intellectual property rights.  
Intel products are not intended for use in medical, life saving, or life 
sustaining applications. Intel may make changes to specifications and product
descriptions at any time, without notice.

Intel is a registered trademark of Intel Corporation. 

*Other names and brands are the property of their respective owners.

Copyright (C) 2023 Intel Corporation.

================================================================================
                                                      ABOUT THIS RELEASE
================================================================================
Build Stamp : SE5C620.86B.02.01.0016
Build Date :  Mar 21,2023
================================================================================
                                                      Supported Platforms
================================================================================
        S2600WFR
		02010016_Production_ACM_TXT_S2600WFR_WFQWF0_CR.bin  
		Checksum:0x5FB6C894
		SFID: 0x294624BD
		02010016_Production_ACM_TXT_S2600WFR_WFTWFS_CR.bin 
		Checksum:0x5FB6C794
		SFID:0xAB02A301
		
        S2600BPR
		02010016_Production_ACM_TXT_S2600BPR_CR.bin
		Checksum:0x61ACE38D
		SFID:0xB04C0A3E

        S2600STR
		02010016_Production_ACM_TXT_S2600STR.bin
		Checksum:0x61AD8F26
		SFID:0xCE173EA8
================================================================================
                                                      BIOS COMPONENTS/CONTENTS
================================================================================
Processors supported: 
        Xeon Scalable Family Processor

Microcode versions:
        CPUID           Version        Status
        0x50654        0x02006e05    (SKX H0) 
        0x50656        0x04003302     (CLX B0)
        0x50657        0x05003302     (CLX B1)

SATAAHCI: 
        v2.00i
VROCSATAEfi: 
        v6.3.0.1005
VROCSATALegacy: 
        v6.3.0.1005
VROCsSATAEfi: 
        v6.3.0.1005
VROCsSATALegacy: 
        v6.3.0.1005
VROC NVMe UEFI drivers: 
        v6.3.0.1005
ESRT2 UEFI drivers: 
        05140000
NVMDIMMDriver: 
        v01.00.00.3536
NVMDIMMHii:
        v01.00.00.3536
AspeedVideo: 
        1.09
ASTVBIOS: 
        1.09
BIOSACM: 
        Production,v1.7.54_LBG
SINIT: 
        Production,v1.7.55_LBG
PDR: 
        V1.0
S2600WFR_WFT_WFS FPKSI:
        v4.10
S2600WFR_WFQ_WF0 FPKSI:
        4.10
S2600BPR FPKSI:
        4.10
S2600STR FPKSI:
        4.10
ME: 
        04.01.04.804
Security Revision:
        0006
HfiPcieGen3:
        v1.9.2.0.0
================================================================================
                                                      INSTALLATION NOTES
================================================================================

WARNING:  It is very important to follow these instructions as they are written.
Failure to update using the proper procedure may cause damage to your system.

1.User can update BIOS flash image via either of the follow methods...
  A. UEFI iFlash32

	1.  Copy the entire contents of the DXXX_Package.zip archive file to the
    	HDD or USB flash drive. (All of the files in the zip archive must reside in the same directory.)
	2.  Boot to UEFI Shell, then change the Shell to mapped device file system
	   Example: Shell> fs0: (or fs1:)
	3.  Run updBios.nsh, updME.nsh, updFD.nsh and reset SUT for each region upgrade respectively.
	4.  Reboot system after the update is completed.
   	5.  Do *NOT* interrupt the BIOS POST during the first boot.

  B. Use flash programmer to burn the new BIOS ROM image into the flash chip.

2.BIOS update under recovery mode as below methods
The USB media is necessary for primary BIOS upgrade and must contain the following files under the root directory, you can capture all the ingredients from BIOS release package:
   1.  UEFI iFlash32 (including IFlash32.efi and ipmi.efi )
   2.  *.CAP( the released BIOS capsule which version you expect to update)
   3.  Startup.nsh (update accordingly to use proper *.CAP file, and NVRAM would be forced update by default)

  A: Install USB media after recovery boot to shell, you need to follow below steps
   1. Under Shell, type "map -r" to map all disc  
   2. Change the Shell to mapped device file system
	   Example: Shell> fs0: (or fs1:)
   3. Execute the startup.nsh scripts for BIOS update, wait for BIOS update complete
   4. Power OFF the system, and revert the recovery jumper position to "normal operation".
   5. Power ON the system. 
   6. Do *NOT* interrupt the BIOS POST during the first boot.
  B: Installed USB media prior to recovery boot
	It will boot automatically into EFI Shell to invoke the Startup.nsh script and start the flash update application (IFlash32.efi). 
	IFlash32.efi requires the supporting BIOS Capsule image file (*.CAP). After the update is complete, there will be a message displayed stating that the
	"BIOS has been updated successfully" indicating the recovery process is finished. The User should then switch the recovery jumper back to normal operation and restart the system by performing a power cycle.

Notes: If to update backup BIOS region, you need to custimize the iflash32 update scripts and add "UpdateBackupBios" parameter 

================================================================================
                                                      BIOS RECOVERY INSTRUCTIONS
================================================================================
The Recovery process can be initiated by setting the recovery jumper (called BIOS Recovery Boot Jumper)

A BIOS recovery can be accomplished from backup BIOS region. 

BIOS starts the recovery process by first loading and booting to the recovery image from backup BIOS region.
This process takes place before any video or console is available. Once the system boots to the recovery image use the following steps to perform the BIOS recovery:
   
   1.  Power OFF the system.
   2.  Switch the recovery jumper. Details regarding the jumper ID and location can be obtained from the Board EPS for that Platform.
   3.  Power ON the system.
   4.  The BIOS POST screen will appear displaying the progress and system automatically 
       boots to the EFI SHELL.
   5.  Follow the BIOS recovery update manual for BIOS recovery.
================================================================================
                                                      IMPORTANT NOTICE
================================================================================
1. R02.01.0009 add KCS Policy Control feature, must combine with BMC which version is equal to or greater than 2.22.59c3b83a. 
2. Starting from BIOS R02.01.0009, when KCS Policy Control Mode is configured as "Deny ALL" on BMC EWS, BIOS cannot be upgraded/downgraded as expected behavior.
3. Due to integrate FPKSI v4.10 into R02.01.0010, need offline flash BIOS binary or use LanConf/nvmupdate to online update the NVM image.    
4. From BIOS 0X020585, online flash BIOS/ME/FD need add Password parameter when Admin PWD is set.
   e.g. (1) Online flash BIOS/ME/FD at EFI Shell using iflash32 tool: iflash32.efi -u BIOS/ME/FD.cap UpdateBackupBios+Password=xxxx -ni;  
        (2) Use OFU tool to update BIOS/ME/FD at OS, please add parameter at CFG file as below: 
	    IMENAME   "ME.cap" Password=xxxx
	    BIOSNAME  "BIOS.cap" UpdateBackupBios+Password=xxxx
            BIOSNAME  "FD.cap" Password=xxxx
	(3) Online Update BIOS/ME/FD through EWS, need enable BIOS setup Option: Server Management->Enforce Password Support.  
    xxxx is the Admin password which set at BIOS setup.
5. Please don't use Ctrl-Alt-Del  to reboot system if user made any BIOS changes, because that method will trigger a warm reboot but BIOS changes need a cold reboot to take effect.					    
================================================================================
                                                      KNOWN ISSUES/WORKAROUND
================================================================================
1. [HSD-ES]: 2103629100 When Flash FSUP from R008 to Can5 with AEP configure,SUT will hang at POST code 32 if reboot system after complete FSUP flash script (only happen @1st time reboot).
   Workaround:
   After FSUP update successfully, do a power cycle using command "Syscfg /gpc" or "Ipmitool –H xxxxxx –U xxxx –P xxxxxx –I lanplus raw 0x30 0x53"
2. [HSD-ES]: 1509856203 BIOS Setup option: Advanced->Memory Configuration->Memory RAS and Performance Configuration: "Correctable Error Threshold" value will change to default(10) after update BIOS from R02.01.0012 to R02.01.0013 and above versions. 
3. [HSD-ES]: 2103649137 [Purley][WFP] Intel I225-T1 NIC FW information not show in BMC Web NIC information page.
4. [HSD-ES]: 2103648077 [STP] RH8.4 & Sles15.3 can NOT boot after BIOS load default when online update BIOS
	 W/A: 1. After RH8.4 installed (UEFI mode), change "Red Hat Enterprise Linux" to be 1st boot option in the BIOS menu by manual. 
	      2. Remove battery to clear CMOS setting, the issue will be fixed.
================================================================================
                                                       CHANGE LIST
================================================================================
                                                        02.01.0016
================================================================================
Rename BIOS ID from 0X.02.0600 to 02.01.0016
================================================================================
							0X.02.0600
================================================================================
[HSD]:[15012936020]CryptoPkg/Library/OpensslLib: Update Open SSL from version 1.1.1j to 1.1.1t to fix new reported BDBA CVEs.	
================================================================================
							0X.02.0599
================================================================================
[HSD]:[2103656951] [STP] System will halt at post code 0X9A after insert raid key.
[HSD]:[2103656856] PurleyPcPkg: Fix EWS capsule update failed with BIOS password.
PurleyPcPkg: Update the copyright year to 2023 for BIOS release
================================================================================
							0X.02.0585
================================================================================
[CCB]:[3616][HSD]:[15011189651] PurleyPcPkg/Restricted: Add new knob "Posted Interrupt Throttle".
	Advance->Integrated IO Configuration->Intel(R) VT for Directed I/0->Eanbled
	Advance->Integrated IO Configuration->Intel(R) VT for Directed I/0->Posted Interrupt Throttle->Enabled
[CCB]:[3617][HSD]:[15011189655] PurleyPcPkg/Restricted: Reduce susceptibility to DDR4 Rowhammer attacks.
[CCB]:[3627][HSD]:[2103652209] PurleyPcPkg/Platform: [CCB 3627]Update IFXTPMUpdate.efi to add support for Infineon SLB9672 TPM firmware update.
[HSD]:[15011189655] PurleyPcPkg/Include: Amend CCB3617 to follow GenerationVariable define rule.
[HSD]:[15012214482] PurleyPcPkg/StitchingPkg: Update VROC EFI driver to version 7.8.0.1012
[HSD]:[14016466448] Revert CpRcPkg/Library/BaseMemoryCoreLib: Improve PPR logging and prevent launch PPR on the same location if not spare rows available
[HSD]:[14016620884] CpRcPkg/Library/BaseMemoryCoreLib: [IPU2022.3 BIOS Candidate][Purley-R][622.D12][Regression] Cannot find PostPackageRepair info in serial log when inject UCE
[HSD]:[14016466448] CpRcPkg/Library/BaseMemoryCoreLib: Improve PPR logging and prevent launch PPR on the same location if not spare rows available
[HSD]:[15011111294] When enable Secure Boot   LT_LOCK bit are 0 if go to the EFI boot path
[HSD]:[15010308440] PurleyPcPkg: [Purley-R][LEGACY] PCH LBG GPP_G17 did not keep its ADR_COMPLETE native function setting across the warm reboot which caused unexpected save/restore flows during the periodical warm reset test with NVDIMM
[HSD]:[22015113608] PurleySktPkg/Library/ProcMemInit: [22.3 Candidate][Purley]Hynix failing DIMM cannot be detected by type 16 and can be detected by AMT 13,14,15 of EWL type 4
[HSD]:[14016284151] PurleySktPkg/Library/ProcMemInit/Chip/Mem/: DDR4 Advanced Memtest Code update for SK hynix to V2.8.7
[HSD]:[14014555453] CpRcPkg/Library/AdvMemTestLib: Unexpected reset when meeting "N1: UpdateRowFailures" and hang at "Invalid Socket Id 0"
[HSD]:[14014548874] CpRcPkg/Library/BaseMemoryCoreLib: EWL logging is missing for UCE PPR using failing DIMM
[HSD]:[14014144524] ServerPlatformPkg/Platform: HSTI update for the TCG event log format
[HSD]:[15010089605] PurleyPlatPkg: Use PchResetPpi for BiosGuard reset
[HSD]:[22013634156] PurleySktPkg/Library/ProcMemInit/Chip/: [CLX] [2020.2 IPU] System got ce/ue errors when toggling  "Volatile Memory Mode" between 1LM and 2LM when AEP dimm was already provisioned to MM
[HSD]:[22014673557] PurleySktPkg/Library/ProcMemInit/Chip/Mem: Memory - 3 Rank Memory 2 way Interleaving through Purley BIOS
[HSD]:[14016298358] PurleySktPkg/Library/ProcMemInit: MEMORY MATRIX SYSTEM (128GB LRDIMM)IS UNABLE TO BOOT with 2400MT/s speed
[HSD]:[14015902887] [PurleyWS22] Lock TXT configuration before running untrusted code
[HSD]:[18021347489] ServerSiliconPkg/CrystalRidge: Subtract 1 from end address in ARS DSM's, so all functions work in the same way.
[HSD]:[15011725908] PurleyPlatPkg/Override: [Purley][BIOS]BIOS should check the password once administrator password is set when performing BIOS online update
[HSD]:[15011564237] PurleyPcPkg/Restricted: Fix Help string of Intel ERST2 of SATA controller shows incorrect.
[HSD]:[15011215801] CpPcRestrictedPkg/PasswordUtilityLib: [DSG][pen-test] No Password Salt or System Wide Salt Used
[HSD]:[15011197631] PurleyPcPkg/Library: Fix PTK0002709: Intel Server BIOS Buffer overflow vulnerability
[HSD]:[16015709660] PurleyPlatPkg: [INTEL-UA-00365] Update memory/io allocation
[HSD]:[14016023993] CpRcPkg/Library/BaseMemoryCoreLib: PPR entries are getting removed in case of  full memory training with IPU2021.2 change
[HSD]:[14016039756] CpRcPkg/BaseMemoryCoreLib: Change to support Renesas Databuffer with AEP
[HSD]:[15011076108] PurleyPcPkg/RasPkg: Fix SKX-CLX LEGACY TARGET_22.1 BIOS log, PPR record, and OS log are not correctly logging primary and buddy banks while inject UC into a VLS region
[HSD]:[14015489456] CpRcPkg/Library/AdvMemTestLib: Revert Micron DRT 3.0 AMT algorithm changes
[HSD]:[22014008124] PurleyPlatPKg: DMI MMIOL_RULE11 value is not correct and overrided by LT baseaddress.
[HSD]:[14015276559] PurleySktPkg/Library/WheaSiliconHooksLib: [IPU2021.1] [VLS] [SKX/CLX][LEGACY][TARGET_22.1] BIOS log, PPR record, and OS log are not correctly logging primary and buddy banks while inject UC into a VLS region
[HSD]:[15010096546] CpPlatPkg/Whea/WheaElog: [TARGET_22.1][CVE-2021-0189] WheaElogSw SW SMI does not check pointers (PTX0001624)
[HSD]:[14014234667] CpRcPkg/Library/AdvMemTestLib, PurleySktPkg/Library/ProcMemInit : Micron requested updated to Advanced Memtest Pattern for Purley
[HSD]:[22012934800] ServerSiliconPkg/MemCpgc: Fix Invert or DC control programming for Purley
[HSD]:[14014868418] CpRcPkg/Library/BaseMemoryCoreLib, PurleySktPkg/Library/ProcMemInit: Program Margin Read to reduced or increased values in case TSE EEPROM CRC failures
[HSD]:[14015056238] CpRcPkg/Library/BaseMemoryCoreLib: RemoveInvalidPprEntry input parameter is Ch in Socket (0 to 7) and PprAddrSetup uses mc Channel (0 to 1)
[HSD]:[22012815450] PurleyPlatPKg: Fix the issue if MeSegSize =0 or DPR size =0 for PostedInterrupt workaround
[HSD]:[2103651081] PurleyPcPkg/GenerationSetup: [DSG] Question value mismatch Option value message will show after  modify BIOS options setting and get back to security or Server Manager page
[HSD]:[1509670376] CpPcRestrictedPkg/UefiOpromSetup: BCM NIC card Oprom is disappeared in UEFI Option ROM control after BIOS load default
[PurleyPC][IPU2022.3] PurleyPcPkg/StitchingPkg:[WFP/BNP]Sync the NvmDimmDriver and NvmDimmHii driver to v01.00.00.3536
[PurleyPC][IPU2022.2] PurleyPcPkg/StitchingPkg:Integrate SPS FW to E5_04_01_04_804_0 to Trunk
[PurleyPC][IPU2022.2] PurleyPcPkg/StitchingPkg:[WFP/BNP]Sync the  NvmDimmDriver and NvmDimmHii driver to v01.00.00.3534
[PurleyPC][IPU2022.2] PurleyPCPkg/StitchingPkg: Intergated Microcode 02006e05 for SKX H0 + change size
[PurleyPC][IPU2022.1] PurleyPcPkg/StitchingPkg:Integrate SPS FW to E5_04_01_04_700_0 to Trunk+spsfiles
[PurleyPC][IPU2022.1] PurleyPcPkg/StitchingPkg:Sync the SINIT version to Production v1_7_55_LBG
[PurleyPC][IPU2022.1] PurleyPcPkg/StitchingPkg:Integrate Microcode 05003302 for clx B1 / 04003302  for clx B0 and  02006d05 for SKX H0 (update).
[PurleyPC][IPU2022.1] PurleyPcPkg/StitchingPkg:Sync the BIOSACM version to Production v1_7_54_LBG.
PurleyPlatPkg: [IPU2021.2]Add Uba support for CVE-2020-8673 Opt out and PurleyR CVE-2020-8673 changes
PurleyPcPkg/Platform/Dxe/WheaElog: [Purley]IPU 2022.1 porting for [TARGET_22.1][CVE-2021-0189] WheaElogSw SW SMI does not check pointers (PTX0001624)
Revert "CpPcRestrictedPkg/PasswordUtilityLib: [DSG][pen-test] No Password Salt or System Wide Salt Used"
PurleyPcPkg/Restricted/Platform/Dxe/GenerationSetup: Add VTD check for Posted Interrupt Throttle knob
PurleyPcPkg/Restricted: fix KW issue
PurleyPcPkg/biosbuild.bat: fix IP clean code build issue
RP release Reference code version:CP_PURLEY_0623_D09.
================================================================================
                                                        02.01.0015
================================================================================
1.Rename BIOS ID from 0X.02.0503 to 02.01.0015
RP release Reference code version: CP_PURLEY_0616_D08.
================================================================================
                                                       0X.02.0503
================================================================================
1.[HSD-ES]:[2103648679]CpPcRestrictedPkg/SetupBmcCfg: SUT can't log in the EWS when a user with a 20 characters password created in the BIOS setup
2.[HSD-ES]:[15010712364]ServerCommonPkg/LogoLib: Update ITK BIOS, reset system, and then System hang up at black screen
3.[HSD-ES]:[2103648106]PurleyPcPkg/RasPkg: fix UCE SEL log error location will change to CPU1 A1 when  enable 'Enhanced Error Containment Mode' and inject UCE on CPU2 DIMM
4.[HSD-ES]:[1509291833]PurleyPcPkg/Restricted: Remove AMT complete without error SEL as request
5.[HSD-ES]:[2103641926]PurleyPcPkg/Uba/UbaMain/Dxe/TypeWolfPass/SmbiosDataUpdateDxe: code update to get NIC card firmware version via Firmware Management Protocol as UEFI spec.
6.[HSD-ES]:[2103648077]CpPcRestrictedPkg/MdeModulePkg: Fix OS boot option disappear after BIOS load default
7.[HSD-ES]:[1509670376]CpPcRestrictedPkg/UefiOpromSetup: BCM NIC card Oprom is disappeared in UEFI Option ROM control after BIOS load default
8.[HSD-ES]:[15010671257][CCB3618]PurleyPcPkg/Platform: [Purley][BIOS]Boot Options must not be removed in case of DIMM error
9.Update the copyright year to 2022 for BIOS release
RP release Reference code version: CP_PURLEY_0616_D08.
================================================================================
                                                        0X.02.0435
================================================================================
1.[BIOS Option Changed][HSD-ES]:[1509878788][Purley_R]Remove “callback” for User Privilege at BIOS setup.
		Server Management->BMC LAN Configuration->User Configuration->Privilege->User/Operator/Administrator/No Access, No Access is default setting;(Remove "Callback")
2.[HSD-ES]:[2103641401][Purley][WFPR]The sensor name about "OEM System Boot Event - Asserted"is wrong.The sensor name should be "BIOS Evt Sensor", BMC2.83 & Frusdr 2.02 sensor name is "OOB FM update".
3.[HSD-ES]:[N/A]PurleyPcPkg/StitchingPkg:Integrate SPS FW to E5_04_01_04_601_0 to Trunk
4.[HSD-ES]:[15010197917][Purley-R][WFP][CCB 3457]BIOS administrator password will not be bypassed when forced_EFI_boot or silent_forced _EFI_boot is detected.
5.[HSD-ES]:[15010325485][WFP][Purley-R]After flashed 0404 BIOS and reboot, there is critical error log in EWS for SPS FW Health and STATUS_LED blinking with orange.
6.[HSD-ES]:[14014516556]CpRcPkg/Library/BaseMemoryCoreLib: [IPU 2021.2] Bit flip within the EEPROM SPD cells
7.[HSD-ES]:[CCB3388][N/A]PurleyPcPkg/RasDxe: CCB3388 Add AMT Completion SEL
8.[HSD-ES]:[N/A]PurleyPcPkg/StitchingPkg:Sync the NvmDimmDriver and NvmDimmHii driver to v01.00.00.3531
9.[HSD-ES]:[N/A]PurleyPcPkg/StitchingPkg:Sync the BIOSACM version to Production v1_7_51_LBG and SINIT version to Production v1_7_51_LBG
10.[HSD-ES]:[N/A]PurleyPcPkg/StitchingPkg:Integrate Microcode 0500320a for clx B1 and 0400320a for clx B0
11.[HSD-ES]:[1509006992]PurleySktPkg: [IPU 2021.2] Reorder BSP to the lowest APICID
12.[HSD-ES]:[N/A]CryptoPkg/OpenSSL: [IPU 2021.2] update OpenSSL to 1.1.1j in submodule
13.[HSD-ES]:[N/A]CryptoPkg/OpenSSL: [IPU 2021.2] Prepare for OpenSSL 1.1.1j upgrade
14.[HSD-ES]:[1509254412][IPU2021.2Beta][Purley-R][Regression][FIXED_IPU2021.2Beta] Ghosted WBINVD breaks CRAM mode loading of ACM, causing SUT to reboot automatically when run getsec64.efi -l SENTER -i with TXT enabled
15.[HSD-ES]:[22013243504]PurleySktPkg/Library/ProcMemInit/Chip: [IPU 2021.2] bad DIMM causes all AEP fail to be mapped to OS , also destroys AEP config
16.[HSD-ES]:[14014175540]PurleySktPkg/Library/ProcMemInit: [IPU 2021.2]Min_ops value is always 0 on various DIMM configs with SKX CPU
17.[HSD-ES]:[18016024150]PurleySktPkg/SouthClusterLbg: [IPU 2021.2][Purley Refresh PCH LBG BIOS] Fixed Eva Lock option
18.[HSD-ES]:[1509092847][IPU2021.1][Purley-R][FIXED_IPU2021.2][LEGACY] "EVA Registers Lock” BIOS option requires "Unlock all PCH Registers"=Disabled (OK) but then has no effect due to BIOS hard-coded to locked.
19.[HSD-ES]:[22012968660]PurleySktPkg/Library/ProcMemInit/Chip/Mem: [IPU 2021.2][Purley-R][IFWI 2021.16.2.28] When memory exceeds MMIOH Base, set 1LM: SUT can't boot normally; set 2LM: can't recognize installed AEP DIMM.
20.[HSD-ES]:[22012950705]PurleyR : [IPU 2021.2] Grantley/Purley potential arbitrary code execution during the Pre-Efi Initialization (PEI)
21.[HSD-ES]:[N/A]CryptoPkg/IntrinsicLib: [IPU 2021.2] Fix possible unresolved external symbol issue
22.[HSD-ES]:[22012713087]Package/Module: [IPU 2021.2] Log EWL4 major = WARN_FPT_CORRECTABLE_ERROR and minorCode = WARN_FPT_PPR_ROW_REPAIR for PPR independent flow
23.[HSD-ES]:[22011708444]CpRcPkg/Library: [IPU 2021.2] Update AdvMemTest EWL Type5 log message to reflect Bank info
24.[HSD-ES]:[14013604560]CpRcPkg/Library/BaseMemoryCoreLib: [IPU 2021.2] Avoid PPR flow for an invalid DIMM entry due to DIMM topology changes
25.[HSD-ES]:[1509006992]PurleySktPkg: [IPU 2021.2] Reorder BSP to the lowest APICID
26.[HSD-ES]:[22012611104]PurleySktPkg/Library/ProcMemInit: [IPU 2021.2] Update MRC DRAM_MIN_OPS table for CLX
27.[HSD-ES]:[14013065992]CpRcPkg/Library/AdvMemTestLib: [IPU 2021.2] System was not able to boot when AdvMemTestOptions are disabled
28.[HSD-ES]:[22011803204]CpRcPkg/Library/AdvMemTestLib, CpRcPkg/Library/BaseMemoryCoreLib : [IPU 2021.2] Track faulty channels per socket
29.[HSD-ES]:[18012660214]: [ME][SPS][IPU 2021.2] HmrfpoExt_GetStatus () 0x03 is not supported in bios
30.[HSD-ES]:[22012325949]PurleySktPkg/Library/ProcMemInit: [IPU 2021.2] Update Advanced Memory Test Pattern for SK Hynix
31.[HSD-ES]:[22011800884]PurleySktPkg/Dxe/CrystalRidge: [IPU 2021.2] CR MGMT Driver does not connect NvmDimmHii Driver
32.[HSD-ES]:[22012225842]PurleySktPkg/Library/ProcMemInit/Chip/Mem: [IPU 2021.2] Memory Map code enters infinite loop if installed system memory exceeds MMIOH Base
33.[HSD-ES]:[22012172123]CpRcPkg/Library/AdvMemTestLib: [IPU 2021.2] Update AMT Pattern for Micron
34.[HSD-ES]:[18014267290][SPS][IPU 2021.2] Nonce bytes can be read from HECI buffer
35.[HSD-ES]:[22012804657]PurleySktPkg/Library/ProcMemInit/Chip/Mem: [IPU 2021.2]PMEM introduction causing random system reboots
36.[HSD-ES]:[15010166283][Purley]espi_smi failed in the log while run "chipsec_main -vv" in windows2022 with chipsec 1.7.1
37.[HSD-ES]:[15010119618][CCB3401][CCB3399][Purley]CCB 3401 Add support for MCTP feature for Purley products
38.[HSD-ES]:[1509955185][Purley-R][CCB 3457][BIOS & BMC]Bypass BIOS admin password when FORCE_EFI_BOOT or SILENT_FORCE_EFI_BOOT is detected
39.[HSD-ES]:[1509918561][Purley-R][CCB 3497][Purley]Update microcode for BNP as customer request
40.[HSD-ES]:[1509377878]PurleyPlatPkg/Acpi: Change RMRR memory reserve type from AcpiNvs to EfiReservedMemoryType.
41.[HSD-ES]:[1509880825][Purley][BIOS]there are lot of NVDIMM ACPI related logs displayed in Serial log even system without NVDIMM connected
42.[HSD-ES]:[22013467511]Create Test BIOS for S2600BP (BNP) with PCIe error detection disabled
43.[HSD-ES]:[1509609474]WFP BIOS faied to update debug(developer) signed capsule when Active region was updated for debug BIOS from recovery jumper
44.[HSD-ES]:[1509776978][Purley_R]SEL record wrong rank when inject SBE in second DIMM with ADDDC mode
45.[HSD-ES]:[14014177411]PurleyPlatPkg/Acpi: Windows OS doesn't boot-up on Wolf Pass with RS3WC080 and VT-d enabled
46.[HSD-ES]:[15010197917]CpPcRestrictedPkg: 3rd patch for bypass BIOS password issue.
47.[HSD-ES]:[16015429421]PurleyPcPkg/Restricted: Hide MCTP options in BIOS Setup to avoid customer confuse as MCTP is not supported from BMC side, and it is not expected that customer to change the options.
RP release Reference code version: CP_PURLEY_0616_D08.
================================================================================
                                                        02.01.0014
================================================================================
1.Rename BIOS ID from 0X.02.0333 to 02.01.0014
RP release Reference code version: CP_PURLEY_0612_D03.
================================================================================
                                                        0X.02.0333
================================================================================
1.[HSD-ES] :[1509670554] PurleyPlatPkg/Platform: WFP SATA Controller will change to "Controller is Disable" after Change QAT to Disable.
2.[HSD-ES] :[CCB3364] PurleyPlatPkg/Platform: Add a hidden knob "Override QAT" to control if to use "GPP_B3_CPU_GP2" to detect QAT.
3.[HSD-ES] :[2103642368] PurleyPlatPkg: Stop bit should be "1" according to new ACPI SPCR spec.
4.[HSD-ES] :[2103641990] CpPcRestrictedPkg/SetupBrowserDxe: Use the BIOS UI to modify the BMC password, it actually does not take effect.
5.[HSD-ES] :[1509426976] CpPcRestrictedPkg/Bds: The copyright should be Copyright (c) 2006-2021 instead of Copyright(c) 2006-2020.
RP release Reference code version: CP_PURLEY_0612_D03.
================================================================================
                                                        0X.02.0328
================================================================================
1.[HSD-ES] :[1508885724] PurleyPlatPkg/ProcessorErrorHandler: [IPU2021.1 PC RAS] Incorrect channel in PPR address after UCE error occur in mirrored backup region
2.[HSD-ES] :[1509245448] PurleyPcPkg/RasPkg: [IPU2021.1 PC RAS] ADDDC should do intra bank VLS when all ranks are unhealthy.
3.[HSD-ES] :[1509203310] PurleyPcPkg/WheaErrorInj: [IPU2021.1 PC RAS] SMI 0x9a mEinjParam address is not correctly passed to OS.
4.[HSD-ES] :[1509231092 1509261012] PurleyPcPkg/RasPkg: [IPU2021.1 PC RAS] Support single-rank bank VLS ADDDC
5.[HSD-ES] :[5388648] PurleyPlatPkg/ProcessorErrorHandler: [IPU 2021.1] [SKX] [CLX] [RAS] Disable fast string from SMI after the first poison detected when EMCA is enabled
6.[HSD-ES] :[22012477418] PurleyPlatPkg/ProcessorErrorHandler: [IPU 2021.1] [IPU-2021.1,Beta][Purley][Regression] Additional PPR entry is logged with incorrect information for DCU error.
7.[HSD-ES] :[22011769652] CpRcPkg/Library/BaseMemoryCoreLib: [IPU 2021.1] [NVDIMM-N] data is lost on warm boot when MRC sets setupChanged to 1
8.[HSD-ES] :[5388662] PurleySktPkg/MemRas: [IPU 2021.1] [RAS] VLS operation uses non healthy rank as buddy rank
9.[HSD-ES] :[5388647] PurleySktPkg/Library/ProcMemInit, CpRcPkg/Library/BaseMemoryCoreLib, PurleyPlatPkg/Platform/Dxe/MemorySubClass :[IPU 2021.1] Fix critical KW Issues in Memory IP code
10.[HSD-ES] :[5388654] CpRcPkg/Library, PurleySktPkg/Library: [IPU 2021.1] Improve how MemTest failure list is being reset
11.[HSD-ES] :[5388609] [CVE-2020-12358] [IPU 2021.1] Attacker can change/crash SMI behavior by modifying the IioUdsData data structure
12.[HSD-ES] :[22011323440] PurleyRpPkg/PurleyPcPkg/AcpiPlatformTableLib/AcpiPlatformLibBdat: [IPU 2021.1] Added EWL to BDAT/ACPI table
13.[HSD-ES] :[5388593] [IPU 2021.1] [RAS] SMI will not be triggered on the new rank with increasing CE count over threshold while another spare copy ongoing in the same memory controller
14.[HSD-ES] :[5388649] PurleySktPkg/ProcMemErrReporting: [IPU 2021.1] [RAS] Ktiviral errors are not handled
15.[HSD-ES] :[5388645] [CVE-2020-24486] [IPU 2021.1] MemSetLocal may overwirte PEI stack
16.[Hsd-ES] :[5388610,1509203310] PurleyPlatPkg/Ras/Whea/WheaErrorInj: [CVE-2020-12360] [IPU 2021.1] SMI 0x9a mEinjParam address is not correctly passed to OS
17.[HSD-ES] :[5388646, 1508362522] PurleySktPkg/MemRas: [IPU 2021.1] Bank reverse VLS should not be allowed when single DIMM ,single rank is present.
18.[HSD-ES] :[5388594, 5388595] PurleyPlatPkg/ProcessorErrorHandler: [IPU 2021.1] Channel and bank information of PPR entry for the UCE PS error is wrong when the error is happening in mirrored backup region
19.[HSD-ES] :[5388658] PurleySktPkg/Library/ProcMemInit: [IPU 2021.1] Avoid MemTest type 17 logs invalid errors on DDR4 DIMMs
20.[HSD-ES] :[5388650] PurleySktPkg/Library, CpRcPkg/Library: [IPU 2021.1] Prevent CPGC Timeout during MemTest
21.[HSD-ES] :[05388630] PurleySktPkg/ProcMeminit: [IPU 2021.1] Support for 1:2 (NM:FM) ratio memory mode configuration for AEP
22.[HSD-ES] :[1508891772] PurleyPcPkg/RasPkg: There is no PPR info record when inject CE error with parameter "PatrolConsume = True"
23.[HSD-ES] :[1509336085] PurleyPcPkg/Roms: The pointers coming from untrusted source can't be overlap or within SMM range.
24.[HSD-ES] :[N/A] PurleyPCPkg/StitchingPkg: Integrate Microcode 02006b06 for SKX H0
25.[HSD-ES] :[N/A] PurleyPCPkg/StitchingPkg: Integrate SPS E5_04_01_04_505_0 to Trunk
26.[HSD-ES] :[N/A] PurleyPCPkg/StitchingPkg: Integrate BIOS ACM 1.7.43 PW and SINIT ACM 1.7.4A PW to purley trunk
27.[HSD-ES] :[N/A] PurleyPCPkg/StitchingPkg: Integrate IntelDCPersistentMemoryDriver v01.00.00.3515 to Trunk
28.[HSD-ES] :[CCB3402] CpPcRestrictedPkg/BootOrder: CCB3402 - Add a new marker line, FORCE_EFI_BOOT_SILENT.
29.[HSD-ES] :[CCB3402] CpPcRestrictedPkg/BootOrder: CCB3402 - Port StartupMarkfileBootorder driver from Whitley
30.[HSD-ES] :[1508841518] PurleyPcPkg/RasPkg: Rank CE Time Window does not work
31.[HSD-ES] :[CCB3364] PurleyPcPkg/Restricted: CCB3364 - Add a new knob to override QAT(Auto(default)/Enable/Disable) to PC generation.
32.[HSD-ES] :[1508841411] PurleyPcPkg/RasPkg: Rank CE will disable after inject 11 times error
33.[HSD-ES] :[1508733401] PurleyPcPkg/RasPkg: SUT will reboot after 3rd strike when do ADDDC test
34.[HSD-ES] :[CCB3356] CpPcRestrictedPkg/Ipmi: CCB3356 - Modify BIOS setup behavior around complex password
35.[HSD-ES] :[16010688351] PurleyPcPkg\Restricted: Please replace BIOS RAID Option "Intel(R) RSTe" to "Intel(R) VROC (SATA RAID)"
36.[Hsd-Es] :[1508961754] PurleyPcPkg/PprVlsErrorLogListener: The debug log will show “[PPR] Entry already existed for” when inject 2nd CE just DIMM slot is different
37.[HSD-ES] :[2103639586] PurleyPcPkg/RasPkg: CCB3390 2nd Patch - ECC error logs will be generated after inject several PPR error on different one by one with BIOS 0X020312
38.[HSD-ES] :[CCB3390] PurleyPcPkg/RasPkg: CCB#3390: Request PPR within SW Error Threshold Flow for new row entries
39.[HSD-ES] :[1508838608] PurleyPcPkg/RasPkg: Handle CSMI during VLS
40.[HSD-ES] :[CCB3389] PurleyPcPkg/RasPkg: CCB#3389: PPR Runtime request SEL event
41.[HSD-ES] :[1508923841] PurleyPcPkg/Restricted: Add "Disable FRB-2 if any bit is enabled" in "Adv MemTest Options" setup help information.
42.[HSD-ES] :[1508895344] CpPcRestrictedPkg/Ipmi: BMC user setup does not report error if input user name is the same as user 14 or user 15 name
43.[HSD-ES] :[1508895086] CpPcRestrictedPkg/Ipmi: BMC user setup does not report error if user2 name input is same as other user such as user3
44.[Hsd-ES] :[CCB3272] PurleyPcPkg/RasPkg: Only record a single SEL entry for a single VLS copy during ADDDC
45.[Hsd-ES] :[1508774126] PurleyPcPkg/RasPkg: Handle SMI and CE Threshold for ADDDC handler
46.[Hsd-ES] :[CCB3245] PurleyPcPkg/Restricted: Log AMT and PPR results in SEL - 2nd Patch
47.[HSD-ES] :[1508779249] PurleyPcPkg/RasPkg: CE error triggered need inject over threshold errors after 2nd waiting for Correctable Error Time window
48.[HSD-ES] :[1508773048] PurleyPcPkg/RasPkg: Bank error counter not clear when reach the time of correctable error time window
49.[HSD-ES] :[1508772732] PurleyPcPkg/RasPkg: SW Bank Threshold, and Time Window only available when PcieErrEn != 0
50.[HSD-ES] :[1508756520] PurleyPcPkg/Restricted: Fix incorrect SEL info for AMT & PPR
51.[HSD-ES] :[1508578905] PurleyPcPkg/Restricted: The help info is not including bit 16 -19 about Adv MemTest Options
52.[HSD-ES] :[CCB3305] PurleySktPkg/Library: Change default SPAREINTERVAL.normopdur and SPAREINTERVAL.numspare.
53.[HSD-ES] :[1508667225] PurleyPcPkg: Enable Samsung and Hynix AMT test
54.[HSD-ES] :[1507980834] PurleyPcPkg/RasPkg: TC2B fourth strike does not intiate any spare action
55.[HSD-ES] :[1507980834] PurleyPcPkg/RasPkg: Fix report incorrect bank number in case rank VLS.
56.[HSD-ES] :[CCB3243] PurleyPcPkg/RasPkg: Improve algorithm for when DSG Commercial BIOS enters VLS mode
57.[HSD-ES] :[2103636701] CpPcRestrictedPkg\Ipmi: The help notes for enable complex password is incorrect in the BIOS setup when set password complexity to "Medium" or "High" in EWS
58.[HSD-ES] :[22011859965] CpPcRestrictedPkg/Library: MCA Recovery (Data Poison) should be enabled by default
59.[Hsd-ES] :[CCB3245] PurleyPcPkg/Restricted: Log AMT and PPR results in SEL
60.[Hsd-ES] :[CCB3030] PurleyPlatPkg/Override: Support Intel DG1 graphic card
61.[Hsd-ES] :[N/A] PurleyPCPkg/StitchingPkg: Revert PeciProxyEnabled and PmBusProxyEnabled from "Integrate SPS E5_04_01_04_505_0 to Trunk"
RP release Reference code version: CP_PURLEY_0612_D03.
================================================================================
                                                    02.01.0013
================================================================================
1.Rename BIOS ID from 0X.02.0291 to 02.01.0013
RP release Reference code version: CP_PURLEY_0610_D02.
================================================================================												   
                                                    0X.02.0291
================================================================================
1.[Hsd-ES]:[14012848534] PurleyPlatPkg/MeUpdate: Remove Do/While Wait Loop after ME Update
2.[Hsd-ES]:[22011661315] PurleyPcPkg/PlatformSetupVariableSyncLib: Leaky bucket interval not triggering when expected
3.[Hsd-ES]:[1508438639] Type 190 offset 05h(slot number) show incorrect value 00 with add-in NIC card installed
4.[Hsd-ES]:[2103635658] After trigger invalid AEP Dimm configuration error, all boot entries are bootable when press F6 to Boot Manager
5.[Hsd-ES]:[2103635506] There is no "Intel Optane(TM) DC Persistent Memory Configuration" option when enter BIOS setup screen
6.[Hsd-ES]:[1508450103] PurleyPcPkg/Platform: Message "Intel (R) Optane(TM) PMem invalid Configuration f" will show during post screen with invalid config
7.[Hsd-ES]:[1508380589] PurleyPlatPkg/Library: Official Optane branding naming and usage update
8.[Hsd-ES]:[2103636919] the host interface will auto enabled after press F10 to save in BIOS setup
9.[Hsd-ES]:[2103636916] boot in BIOS setup->server management->BMC LAN Configuration will pop a warning messages when disable host interface in EWS
RP release Reference code version: CP_PURLEY_0610_D02.													   
================================================================================
                                                     0X.02.0284
================================================================================
1.[BIOS Option Changed][Hsd-ES]:[1508380589] change the name "DCPMM" Update to "Intel(R) Optane(TM) PMem".(Main->memory configuration; Advanced->memory Configuration->DIMM information)
2.[BIOS Option Changed][Hsd-ES]:[CCB3178] - Enable Advanced MemTest
		(Adavnced->memory Configuration->MemTest->Auto/Disabled/Enabled, Auto is defalut setting;
	     	Adavnced->memory Configuration->MemTest Loops, 1 is defalut setting;
		 Adavnced->memory Configuration->Adv MemTest Options, 0 is defalut settings;
		 Adavnced->memory Configuration->Adv MemTest Reset Failure Tracking List ->Disabled/Enabled.Disabled is defalut settings;
		 Adavnced->memory Configuration->Adv MemTest Conditions->Disabled/Auto/Manual. Auto is default settings)
3.[BIOS Option Changed][Hsd-ES]:[CCB3158] Integrate BMC features developed by InSyde,add below settings at BIOS setting UI
         	(Server Management->BMC LAN Configuration->HI BMC LAN configuration
		 Server Management->BMC LAN Configuration->HI Host LAN configuration)
4.[BIOS Option Changed][Hsd-ES]:[1508332492]  change System time default value from 2015/01/01 to 2020/01/01(main->System Data)
5.[Hsd-ES]:[1508383190] CpPcPlatPkg/SmiVariable: Memory overlap in VariableInterface SMI
6.[Hsd-ES]:[CCB3275] Enable NIC 190 and Storage(NVMe) 194 SMBIOS Table
7.[Hsd-ES]:[1507934020] Hide BMC and SDR version info under KCS Deny All mode
8.[Hsd-ES]:[1508375971] PurleyPcPkg/BuildImage.bat: (Patch 2)CAPSULE_ME.cap and CAPSULE_FD.cap are not available for IP Clean Build after IPU2020.2 Integration
9.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Sync the RSTE drivers and VMDVROC version to v6.3.0.1005
10.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Microcode 02006a08 for SKX H0
11.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Microcode 05003003 for CLX B1
12.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate SPS E5_04_01_04_423_0 to Trunk
13.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Microcode 04003003 for CLX B0
14.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate IntelDCPersistentMemoryDriver v01.00.00.3506 to Trunk
15.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate SINIT 1.7.49 PW
16.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate ACM 1.7.41 PW to purley trunk
17.[Hsd-ES]:[2103633362] PurleySktPkg/Include: Fix Build Error Caused by HSD 2103633362 (WHEA ID # 47/23 and Correctable error show when inject uncorrectable non-fatal error via wheahct)
18.[Hsd-ES]:[5388637] PurleySktPkg\ProcMemInit: Fixed Memtest issues with NVDIMM-N restore flow
19.[Hsd-ES]:[5388638] PurleySktPkg\ProcMemInit: Added Refresh Watermarks control to Memtest step
20.[Hsd-ES]:[5388628, 1508197968] PurleySktPkg/MemRas: ADC first strike meet ECC +1 with 1DPC 1RX4
21.[Hsd-ES]:[1508244875] PurleySktPkg/ProcMemErrReporting: Continuously Inject second strike CE directly cause RankVLS(reverse), and cause cor_err_cnt beyond threshold.
22.[Hsd-ES]:[14012345009] PurleySktPkg/MemDecode: SUT cannot boot into OS after enable "Mirror TAD0".
23.[Hsd-ES]:[18012748461] [ME] Platform code should not verify HECI interface
24.[Hsd-ES]:[5388371] FW-UEFI-Vuln-2019-132 Unsecure write to SMRAM because of missing buffer validation
25.[Hsd-ES]:[5388631] PurleySktPkg/ProcMemInit: PPR flow is triggered for several failing rows within the failed Rank0
26.[Hsd-ES]:[5388626, 14012151686, 1508197968] [RAS]: mSystemMemoryMap->Socket[Socket].ChannelInfo is still  pointing to boot time memory and  used in runtime code
27.[Hsd-ES]:[5388607] PurleySktPkg\ProcMemInit: Updated Advanced Memtest vendor content
28.[Hsd-ES]:[5388625] CpRcPkg/AdvMemTestLib: [AdvMemTest] Rank1 shows all DQs got failures in MemTestScram retry path
29.[Hsd-ES]:[5388624] CpRcPkg/AdvMemTestLib: [AdvMemTest] System reboot unexpectedly upon "N1: UpdateRowFailures: New failure occured in previously masked range"
30.[Hsd-ES]:[5388623] IPU 2020.2 Beta [SKX-H0]-Purley - PIV_IPU_PatrolScrubDowngrade_Enable_Logging_Signaling_UCE_EMCAGen1_L - UCE error is injected by CScripts but is no logged in Serial output or OS either
31.[Hsd-ES]:[5388449] ProcMemInit/Chip: UCE in ADDDC due to incorrect sparing of unmapped DRAM memory.
32.[Hsd-ES]:[5388621] CpRcPkg/AdvMemTestLib: CpRcPkg/AdvMemTestLib: Bug Fixes for AdvMemtest
33.[Hsd-ES]:[5388525, 5388620, 1508101191, 1508188532, 1508129395] [SKX][RAS] Tc3b met SMI dead lock issue after strike 3 to overflow with ADDDC enable and SDDC plus one disable.
34.[Hsd-ES]:[5388617] PurleySktPkg/ProcMemInit: [CMD Vref TF] Skip MA 13,14, 15, 16 for DDRT DIMMs only in 2DPC config in the late cmd clock and skip teh same in RMT
35.[Hsd-ES]:[5388608] PurleySktPkg/Library/ProcMemInit/Chip/Mem: [CLX/AEP]BIOS incorrectly logs WDB flush failed on cold reset
36.[Hsd-ES]:[5388604] AdvacentMemTest row failure bit 18 being reported as part of C[2:0]
37.[Hsd-ES]:[5388601]CpRcPkg/AdvMemTestLib: Restore refresh after MemTest
38.[Hsd-ES]:[5388592] CpRcPkg\AdvMemTestLib: Resolved Advanced Memtest failure in TestType 16 after PPR repair and retry
39.[Hsd-ES]:[5388587] SDC on running CAP+ Memicals
40.[Hsd-ES]:[5388431] CpRcPkg\AdvMemTestLib: Added Advanced Memtest support for DRAM vendor-specific algorithms
41.[Hsd-ES]:[5388492] [RAS] : Change the BIOS help text for Patrol Scrub knob
42.[Hsd-ES]:[5388583] Basetool: Fix GCC build Target failures in PreFl
43.[Hsd-ES]:[5388533,5388548,5388529,5388528,5388527,5388514,5388532] [RAS] SMI generation being disabled during ADDDC spare copy..
44.[Hsd-ES]:[5388577] ServerPlatformPkg/TPM: add platform hierarchy configuration
45.[Hsd-ES]:[5388552] PurleyPlatPkg/WheaErrorInj: Patrol Scrub APEI EINJ memory-uncorrectable-non-fatal (0x10) and TRIGGER=1 fails to work with serial printing disabled (ordering/delay related issues)
46.[Hsd-ES]:[5388573] Restore "Bank XOR" setup option to prevent memory bandwidth degradation in Linux.
47.[Hsd-ES]:[5388575] unsafe shutdown being logged by aep when a warm reboot is followed be a cold boot initiated by mrc error handling
48.[Hsd-ES]:[5388545]] ServerSiliconPkg/MemTurnaroundTimingLib: Rank Switch Fix: Equation Check for DDR-T Turnarounds
49.[Hsd-ES]:[5388557] [RAS] Add BIOS setup opton to enable/disable patrolscrub UC downgrade signaling to Corrected
50.[Hsd-ES]:[5388574] PurleyPlatPkg: Rank Switch Configuration : Set Default to RCVEN_AVE
51.[Hsd-ES]:[538855] [RAS] Remove the patrol scrub option added to pc package header files.
52.[Hsd-ES]:[5388570] PurleyPlatPkg: Rename Rank Switch setup knob
53.[Hsd-ES]:[5388569] Purley/PurleyRpPkg: Update PurleyR IPClean tools in release folder per BDBA analysis (Phase 3)
54.[Hsd-ES]:[5388566] [RAS] UCE Error detected by patrol scrub is should be logged as uncorrected error
55.[Hsd-ES]:[5388567] Resolve microcode revision checking issue in BIOS
56.[Hsd-ES]:[5388522] Patrol Scrubber needs to be turned OFF with ADR flow (CCB follow up)
57.[Hsd-ES]:[5388555]AEP-Media error caused by illegal access issue
58.[Hsd-ES]:[5388554] PurleySktPkg/MemDecode: Wrong TAD programming when rank 0 is disabled.
59.[Hsd-ES]:[5388484] ServerCommonPkg/LogoLib: FW-UEFI-Vuln-2019-179 Use of unsafe deprecated function ConvertBmpToGopBlt
60.[Hsd-ES]:[5388395]CLONE from skylake_server: AEP - Define 1018 namespaces leads to reboot loop"
61.[Hsd-ES]:[5388486] Package/Module:FW-UEFI-Vuln-2019-183 SMM accessing memory outside of SMRAM and not validating the memory
62.[Hsd-ES]:[5388407] Package/Module: Update PurleyR IPClean tools in release folder
63.[Hsd-ES]:[14010619471,5388537] PurleyPlaPkg: add TXT event log
64.[Hsd-ES]:[5388546] Rank Switch Fix: Rcven Ave part2 performance issue when RMT enabled
65.[Hsd-ES]:[5388485] Package/Module: Out of Bounds memory writes
66.[Hsd-ES]:[5388544] PurleySktPkg\ProcMemInit: Added "Refresh Watermarks" option for Row Hammer migation
67.[Hsd-ES]:[5388539] Linux cannot load acpi-frequency driver when X2APIC and VT-d are enabled
68.[Hsd-ES]:[5388534] PurleyPlatPkg/ProcessorErrorHandler: IPU [SKXH0 602.D02] UCE Error detected by patrol scrub is logged as corrected error(Expectation: Signaling as CE while logging as UCE)
69.[Hsd-ES]:[5388489]PurleyPlatPkg/Me: ME BIOS: AMT: Unable to Retrieve Hardware Information
70.[Hsd-ES]:[5388440] bios changes required for purley/purleyr to enhance p2p perf
71.[Hsd-ES]:[5388520] PurleySktPkg/Dxe/CrystalRidge: Fixing potential security issue with
72.[Hsd-ES]:[5388492] [RAS] : Revise BIOS knob PatrolScrub: Enable. Disable, Enable at End Of POST
73.[Hsd-ES]:[5388535] CpRcPkg\BaseMemoryCoreLib: Added MRC improvements to the "Rank Switch Fix"
74.[Hsd-ES]:[5388525] [Purley][RAS]:DXE Assert when per-rank CECC counters artificially set to threshold
75.[Hsd-ES]:[5388531] PurleyPlatPkg/OemProcMemInitLib: Missing NFIT type 6 (Flush Hint Address) table for AEP DIMM
76.[Hsd-ES]:[5388515] CpRcPkg\BaseMemoryCoreLib: Added MRC options for "Rank Switch Fix"
77.[Hsd-ES]:[5388513] PurleySktPkg/ProcMemErrReporting: For the UCE PPR log, fix the code for incorrect Rank when the Dimm is on slot1
78.[Hsd-ES]:[5388501] CpRcPkg\AdvMemTestLib: Fixed false failures and hang conditions in Advanced Memtest
79.[Hsd-ES]:[5388473] kernel panic observed when executing DCU test with eMCA Gen2 enabled
80.[Hsd-ES]:[2103633735] PurleyPcPkg/Ipmi/GenericIpmi: In BMC force update mode,the KCS mode of the BIOS setup still show allow all mode in the restricted/deny all mode
81.[Hsd-ES]:[22011363805] CpPcRestrictedPkg\Include: ADDDC threshold, when set to 500d (1F4h), is triggering after 244d (F4h)
82.[Hsd-ES]:[1508195797] PurleyPcPkg/SmbiosDataUpdateDxe: Type 190 NIC Firmware version is incorrect
83.[Hsd-ES]:[CCB3141] Some BIOS settings, when modified by ITK, don't take effect until the user manually intervenes
84.[Hsd-ES]:[1508203382]  PurleyPcPkg/Uba/UbaMain: SMBIOS type 41 video device bus number is incorrect
85.[Hsd-ES]:[2103633770] CpPcRestrictedPkg/SetupBmcCfg: Pop up warning message when user password cannnot meet complex requirements
86.[Hsd-ES]:[2103633158] PurleyPcPkg/Uba: STP PCIE Retimer NVME SSD can NOT be detected correctly after AC off/on cycle
87.[Hsd-ES]:[2103634038] PurleyPlatPkg/XmlCliRestricted/XmlCliCommon: BIOS Setup-->Main page has setting “POST errors Pause” but EWS BIOS Configurations Main page do not have it
88.[Hsd-ES]:[2103633809] CpPcRestrictedPkg/Library/CommonSetupLib/: "<"and">"symbol display as"?"in EWS->BIOS Configurations->Integrated IO Configuration.
89.[Hsd-ES]:[CCB3157] Memory SMBIOS record Asset Tag to show memory manufacturer date from SPD
90.[Hsd-ES]:[1508192389] PurleyPcPkg/Uba/UbaMain: SMBIOS type 8 internal reference designator string of RAID KEY mismatch with the motherboard
91.[Hsd-ES]:[1508192256]  PurleyPcPkg/Uba/UbaMain: SMBIOS type 8 internal reference designator string of M2 PCIE sSATA ports mismatch with the motherboard
92.[Hsd-ES]:[2103626923] PurleyPcPkg/Uba: Fix SMBIOS type9 “Current Usage” information is incorrect when only one CPU connect.
RP release Reference code version: CP_PURLEY_0610_D02.													   
================================================================================
                                                        02.01.0012
================================================================================
1.Rename BIOS ID from 0X.02.0256 to R02.01.0012
RP release Reference code version: CP_PURLEY_0602_D02.
================================================================================
                                                        0X.02.0256
================================================================================
1.[Hsd-ES]:[2207406475] Intel Server System S2600WF Vulnerable SMI handler UsbRt pointed to HwSmiHandler
2.[Hsd-ES]:[NA] Integrate Microcode 02006906 for SKX H0
3.[Hsd-ES]:[NA] Integrate Microcode 05002f01 for CLX B1
4.[Hsd-ES]:[NA] Integrate Microcode 04002f01 for CLX B0
RP release Reference code version: CP_PURLEY_0602_D02.
================================================================================
                                                        0X.02.0245
================================================================================
1.[Hsd-ES]:[1507959901] Change Mailbox register to SIO scratch pad register 0x20
2.[Hsd-ES]:[CCB3115] Change the default vaule of NVM Performance Setting
3.[Hsd-ES]:[1507879137] CCB3027 Enable PPR Type in BIOS setup knobs
4.[Hsd-ES]:[NA] Integrate SPS E5_04_01_04_381_0 to Trunk
5.[Hsd-ES]:CCB3015 Add PCIe port option ROM control in UEFI mode.
6.[Hsd-ES]:[2103630638] Handling au-reboot after injecting 2nd ADDDC error for standard RAS
7.Merge remote-tracking branch 'remotes/origin/PurleyRefresh_PC_20Q2_QSBR' into Purley-R_DSG_BIOS_Production_Trunk
8.[Hsd-ES]:[1507892509] Update BIOS OOB update&config SEL
9.[Hsd-ES]:[1507864848] Replace BIOS RAID Option "Intel(R) RSTe" to "Intel VROC" for sSATA
10.[Hsd-ES]:[1507927108] Update SMBIOS Type 17 AssetTag on WolfPass.
11.[Hsd-ES]:[NA] Integrate Microcode 04002f00 for CLX B0
12.[Hsd-ES]:[2103630333] Modified the EWS BIOS configuration "Reset Static Boot Order" value from 0x0 to 0x1 will cause SUT reboot continuously
13.[Hsd-ES]:[1507924351] Fix incorrect processor info in setup.
14.[Hsd-ES]:[NA] Sync the RSTE drivers and VMDVROC version to v6.2.0.1034
15.[Hsd-ES]:[NA] Integrate SINIT 1.7.48 PW
16.[Hsd-ES]:[NA] Integrate SPS E5_04_01_04_381_0 to Trunk
17.[Hsd-ES]:[NA] Integrate Microcode 05002f00 for CLX B1
18.[Hsd-ES]:[1507659391] Fix to SMBIOS Type 197 offset 6 and offset 7
19.[Hsd-ES]:[1507894757] Some knobs still can be modify and some Sub_Menu knobs can't be read with user password entering
20.[Hsd-ES]:[NA] Integrate Microcode 02006901 for SKX H0
21.[Hsd-ES]:[NA] Integrate IntelDCPersistentMemoryDriver v01.00.00.3497 to Trunk
22.[Hsd-ES]:[NA] Integrate ACM 1.7.40 PW to purley trunk
23.[Hsd-ES]:[2103630341] The Multi-Rank Sparing value of EWS is not match with BIOS setup menu.
24.[Hsd-ES]:[5388518] Fix CMOS Corruption
25.[Hsd-ES]:[5388517] SYSTEM_CONFIGURATION structure MUST NOT have changes in the middle of the structure
26.[Hsd-ES]:[5388476] Request to add new profile for 2LM performance improvement
27.[Hsd-ES]:[5388463] Fixed incorrect bank address reported by Advanced Memtest
28.[Hsd-ES]:[5388474] Fatal event (PCC=1) with eMCA Gen2 enable causes the system to not boot
29.[Hsd-ES]:[5388088] CLX-AP code enabling in IP clean tree
30.[Hsd-ES]:[5388498] Fixed Soft PPR flow
31.[Hsd-ES]:[5388490] The MBP buffers must be cleared before exiting functions
32.[Hsd-ES]:[5388493] [ME][AMT] Corrected the media table length
33.[Hsd-ES]:[5388487] Need Panic and Watermark change setup option for MRC
34.[Hsd-ES]:[5388458] ADDDC SMI handler's writes to non-32 bit aligned registers failing on CLX"
35.[Hsd-ES]:[5388429] CE and UC Error Injection Shows Wrong DIMM Location in AD-WB or 2LM Provisioning
36.[Hsd-ES]:[5388482] Fix Surprise reset and Multi Socket Bug
37.[Hsd-ES]:[5388488] Fixed Memtest failures during the PPR flow
38.[Hsd-ES]:[5388472] [CLX][ADDDC]BIOS sets nonfailed_cs to non-existent rank in 3-rank config
39.[Hsd-ES]:[5388483] Enabled the DDR scrambler prior to Legacy Memtest
40.[Hsd-ES]:[5388470] Remove the TRFC1_VAL tRFC override for SPD_16Gb DIMMs introduced by sighting 5387664
41.[Hsd-ES]:[5388479] PBF should not affect HWPInterrupt and EPPEnable settings
42.[Hsd-ES]:[5355343] UCE in ADDDC due to incorrect sparing of unmapped DRAM memory.
43.[Hsd-ES]:[5388454] Pistachio PRT:  prevent nested machine check, demote P.S UC to signal corrected
44.[Hsd-ES]:[5388456] IO resource overlap between PNP0C02 and IPI0001 devices
45.[Hsd-ES]:[5388467,5388468] Update PPR RAS code to fix the DRAM Mask reporting for x8 DIMMS and also reporting multiple entries for same address
46.[Hsd-ES]:[5388443] CPU SystemSemaphore0 Will Not Release Semaphore And Appears Stuck
47.[Hsd-ES]:[5388471] Added Receive Enable Average feature
48.[Hsd-ES]:[5388441] AppDirect in CPU SKU memory cap exceeded boots with Non-Functional DCPMMs
49.[Hsd-ES]:[5388464] [RAS] EINJ code is causing to have SDC under mirror mode
50.[Hsd-ES]:[5388435] Fixed TOC/TOU vulnerability
51.[Hsd-ES]:[5388452]  Fixed Advanced Memtest failure where DQ mask is all 0xFFs
52.[Hsd-ES]:[5388399] [PurleyRefresh] Extend the Direct Update Flow (HMRFPO) to support partial Update via SMI handler
53.[Hsd-ES]:[5388390] ME Update system reset when using OFU build 14.1 Build 21 with WW18 BKC
54.[Hsd-ES]:[2103626444] SUT will reset after udpate BIOS/FD/ME via OFU in Linux
55.[Hsd-ES]:[5388459] AEP-64GB SKU - fail to boot in AD mode (2-2-2)
56.[Hsd-ES]:[5388457] illegal access error seen when upgrading from BKC16 to 26 @ DPA 0x1040
57.[Hsd-ES]:[5388430] [MSFT] [AEP] [AD/WB] NM UC error causes AD-WB NM flush hang
58.[Hsd-ES]:[5388455] Pistachio RCVEN training result offset
59.[Hsd-ES]:[5388451] Bug fixes for Advanced Memtest with PPR
60.[Hsd-ES]:[5388428] update for memory corruption below 1MB on S3 resume
61.[Hsd-ES]:[5388444] Add CTLE functionality for Nanya DRAM based DIMMS
62.[Hsd-ES]:[5388438] Fix CE PPR Error flow
63.[Hsd-ES]:[5388391] Added Advanced Memtest feature with Post Package Repair
64.[Hsd-ES]:[5388439] ServerSiliconPkg/PeiPchIinitLib Incorrect Flexible IO Adapter (FIA) used to map Pcie port clocking
65.[Hsd-ES]:[5388396] Added memory RAS support for UCE->PPR flow
RP release Reference code version: CP_PURLEY_06012_D03.
================================================================================
                                                        02.01.0011
================================================================================
1.[Hsd-ES]:Rename BIOS ID from 0X.02.0225 to R02.01.0011
RP release Reference code version: CP_PURLEY_0596_D08.
================================================================================
                                                        0X.02.0225
================================================================================
1.[Hsd-ES]:[NA]Fix ISS sync between BIOS and BMC
2.[Hsd-ES]:[1507819944] Fix password mismatched bug
3.[Hsd-ES]:[14010920676] RAID module RMS3HC080 and Software RAID RSTe can't work together in legacy mode
4.[Hsd-ES]:[16010688351] Replace BIOS RAID Option "Intel(R) RSTe" to "Intel VROC"
RP release Reference code version: CP_PURLEY_0596_D08.
================================================================================
                                                        0X.02.0204
================================================================================
1.[Hsd-ES]:[2103626900] Fix incorrect behavior after injecting PCIe CE/UCE on Port C
2.[Hsd-ES]:[1507176793] Hardware P States disable function invalid when set "Hardware P States disable +Active PBF enable" in BIOS.
3.[Hsd-ES]:[1507588040] Fix Incorrect RMRR of Raid Card (RMS3HC080) in DMAR
4.[Hsd-ES]:[1507243669] Fix Incorrect Console Redirection Display of 100*31
5.[Hsd-ES]:[2103626914] Add 3 invalid DCPMM config and change "promotewarning" to false by default.
6.[Hsd-ES]:[NA] Fix PC IssCapable cannot be changed back to 0
7.[Hsd-ES]:[no sighting] Change copyright to 2020.
8.[Hsd-ES]:[NA]Merge branch 'Purley-R_DSG_BIOS_Production_Trunk' of ssh://git-amr-7.devtools.intel.com:29418/iafw-purley into Purley-R_DSG_BIOS_Production_Trunk
9.[Hsd-ES]:[1507430586] Open some RP setup items.
RP release Reference code version: CP_PURLEY_0596_D08.
================================================================================
                                                        02.01.0010
================================================================================
1.Rename BIOS ID from 0X.02.0141 to R02.01.0010
RP release Reference code version: CP_PURLEY_0596_D08.
================================================================================
                                                        0X.02.0141
================================================================================
1.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Fpksi v4.10_80001A7A_WFT_WFS/v4.10_80001A76_BNP/v4.10_80001A78_STP/v4.10_80001A79_WFQ_WFO.
RP release Reference code version: CP_PURLEY_0596_D08.                                                      
================================================================================
                                                        0X.02.0136
================================================================================
1.[Hsd-ES]:[1507430586] CCB#2762 SMBIOS region shall include additional structure (type 210) for Intel Speed Select Configuration.
2.[Hsd-ES]:[HSD-ES bug id] Fix incorrect PCIe Slot Number in SMBIOS type 192
3.[Hsd-ES]:[1609246698] Change "Enforced Password Support" to disable after clearing admin PWD
4.[Hsd-ES]:[1507430586] Adjust some information of SMBIOS Type210.
5.[Hsd-ES]:[1507492512] CCB#2707: Customer ask for a way/tool to change SMBIOS Type0- BIOS Vendor String from Intel to DataON
6.[Hsd-ES]:[2103627193] Some of SMBIOS T197 info is incorrect.
7.[Hsd-ES]:[2103626917] Fix incorrect port index in SMBIOS type 190
8.[Hsd-ES]:[1608803208] Enable WheaErrorInjSupportEn for CR Build
9.[Hsd-ES]:[1507520209] Fixed incorrect description of "AtomicOp Egress Blocked Mask"
10.[Hsd-ES]:[2103626884] FRB2 triggered on the early video phase.
11.[Hsd-ES]:[2103629389] Send BIOS ID to BMC in RSD module
12.[Hsd-ES]:[2103629034] Fix ISS cannot be changed in BIOS setup in "DenyAll Mode"
RP release Reference code version: CP_PURLEY_0596_D08.
================================================================================
                                                        0X.02.0094
================================================================================
1.[Hsd-ES]:[5388392] CLONE from skylake_server: [Microsoft] System hang when injecting poison when in ADWB.
2.[Hsd-ES]:[5388371] FW-UEFI-Vuln-2019-132 Unsecure write to SMRAM because of missing buffer validation.
3.[Hsd-ES]:[5388403] CLONE from skylake_server: [S3] DDRT ERID/Rd error during S3 resume.
4.[Hsd-ES]:[5388406] CLONE from skylake_server: [S3] AEP Dimms & other devices get reset during S3 resume.
5.[Hsd-ES]:[5388405] [S3] Hang with CatErr - DDR4 UNC / Petrol scrub unc during S3 transition restoration.
6.[Hsd-ES]:[FIV11876] PurleyPCPkg/StitchingPkg:Integrate IntelDCPersistentMemoryDriver v01.00.00.3475 to Trunk.
7.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate SPS E5_04_01_04_339_0 to Trunk.
8.[Hsd-ES]:[5388394] Combo RC failing to training LRDIMMs.
9.[Hsd-ES]:[5388416] [Purley-R][Power Management] BIOS knob "TCC Activation Offset" Not Functional.
10.[Hsd-ES]:[] PurleyPlatPKg: PRT workaround
               (1)Address map is changed to swap[TSEG+DPR] and MSEG order in the address map
               (2)TOLM setting remains same on CHA, but changed on PCIe (below MESEG) and DMI (above MESEG)
               (3)MMIOL_RULE[11] on IIO stacks is changed to cover [TSEG +DPR] on DMI and [TSEG+DPR+MESEG] on PCIe pointing to another stack on the same socket
               (4)Zero out TSEG.LIMIT and LTDPR.size on all IIO stacks and MENCMEM.LIMIT on all PCIe stacks
               (5)Change TGT_LIST1.MMIOL11 on each IIO stack to point to another IIO stack on local socket
               (6)Include the change for handling uncorrected memory errors from Pawel
11.[Hsd-ES]:[5388413] TxLRDIMMDqCentering should only run for 2933 and above.
12.[Hsd-ES]:[5347339] [Purley-R][CR_2S][IFWI:2019.32.3.06] Viral Status cannot be set after Inject Three strike to trigger viral mode.
13.[Hsd-ES]:[5388414] TrainDramRxEq and ModifiedTrainCTLE need to run for 2933 and above only.
14.[Hsd-ES]:[5388377] MCA recovery reports wrong failed DIMM location on FC29.
15.[Hsd-ES]:[5388420] CK Stop exit potentially can cause DRAM read ECC errors with IDT Gen 2.5 C2 Data Buffer.
16.[Hsd-ES]:[5388384] PurleySktPkg Override CpuMpDxe: Make PpinCtl feature to follow the flow.
17.[Hsd-ES]:[NA] PurleyPcPkg/RasPkg: Report MEM UCE inside MESEG region.
18.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Microcode 02000065 for SKX H0.
19.[Hsd-ES]:[CCB#2798] PurleyPcPkg/Restricted: Expose x2APIC option in BIOS Setup menu.
20.[Hsd-ES]:[NA] PurleyPcPkg/Uba: When OCP card is installed, there are two type41 records for 000:3d:00.0.
21.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Microcode 0400002c for CLX B0.
22.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate Microcode 0500002c for CLX B1.
23.[Hsd-ES]:[1507469348] CpPcRestrictedPkg/Variable/SmiVariable: Fix Bug of "Race conditions in VariableInterface()".
24.[Hsd-ES]:[5388272] Package/Module: Update for new ucode.
25.[Hsd-ES]:[1507473345] PurleyPlatPkg/Rsa: Skip adding SMBIOS type 210 when ISS is not supported.
26.[Hsd-ES]:[2208222019] CpPcRestrictedPkg/Tools/GenSFID2/: Fix Potential Memory Leak in GenSFID2.
27.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate ACM 1.7.32 PW to purley trunk.
28.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate SINIT 1.7.45 PW.
29.[Hsd-ES]:[NA] PurleyPCPkg/StitchingPkg: Integrate SPS E5_04_01_04_339_0 to Trunk.
RP release Reference code version: CP_PURLEY_0596_D08.
================================================================================
                                                        02.01.0009
================================================================================
1.[Hsd-ES]:[1507429579]Prompted BIOS ID to webpost R02.01.0009
================================================================================
                                                        0X.02.0083
================================================================================
1.[Hsd-ES]:[2103628766] Integrate SPS E5_04_01_04_296_0 PTU files to replace  SPS E5_04_01_04_323_0 PTU files
2.[Hsd-ES]:[2103626250] SUT will hang on black screen when use NVMe SSD then install windows chipset driver
3.[Hsd-ES]:[2207690589] Unreleased product code names and build paths retrievable in capsule files.
4.[Hsd-ES]:[5388345] CLONE from skylake_server: 6 sec time window from MB3 (EKV entering normal mode) to iMC entering normal mode - SCS
5.[Hsd-ES]:[CCB2763] [BIOS/BMC Q3'19] Single reboot to update BIOS, FD, ME & BMC: Current design requries 3 reboots to update FD,  BIOS and ME. Unacceptable customer experience. Need to reduce to one boot only.
6.[Hsd-ES]:[5388220] CCB 136637 OS Mgmt: AEP fallback to SMBus when DDRT training fails to allow log collection & firmware upgrade
7.[Hsd-ES]:[5388361] CCB 136533 AEP SW RAS: BIOS Driven "BACKGROUND" ARS thread - critical for proper Windows/Azure error handling behavior (phase 2)
8.[Hsd-ES]:[5388220] CCB 136637 OS Mgmt: AEP fallback to SMBus when DDRT training fails to allow log collection & firmware upgrade
9.[Hsd-ES]:[5388223] CCB 136654 Clear PCD0 corruption without overwrite DIMM
10.[Hsd-ES]:[5388342] PurleyPlatPkg/WheaErrorInj: MCA Recovery Test Issue with 6133 CPU
11.[Hsd-ES]:[5387495] CCB 136533 AEP SW RAS: BIOS Driven "BACKGROUND" ARS thread - critical for proper Windows/Azure error handling behavior
12.[Hsd-ES]:[5388325] Short ARS - Allows errors to be returned even user requested no notification.
13.[Hsd-ES]:[5388097] PurleySktPkg/Iio: Save S3 boot script for IOAPIC   There was an issue with missing some PCIE graphic cards after S3 resume.
14.[Hsd-ES]:[2103626817] PurleyPcPkg/Restricted: The KTI Prefetch item help text is different BIOS spec. The prefetch letter p in KTI prefetch should be capitalized.
15.[Hsd-ES]:[5388323] PurleyPlatPkg/Me: User CAPS State for WS in support of Purley R CCB 136665
16.[Hsd-ES]:[5388342] PurleySktPkg/Library/ChipsetErrReporting: IRPPERRSV CSR maps protocol parity errors to correctable
17.[Hsd-ES]:[5388338] CLX64L - Enabling CLTT w/PECI results in both CLTT mode and CLTT w/PECI
18.[Hsd-ES]:[5388350] [IPS 1409117089][AMI] x2APIc broken
19.[Hsd-ES]:[5388309] PurleyPlatPkg\Platform\DxeSmm\BiosGuard: Vuln-2019-012 -- Unregister IO trap once triggered
20.[Hsd-ES]:[5388326] Incorrect DIMM location reported when disabling CMCI-SMI Morphing in 2LM
21.[Hsd-ES]:[5388356] PCU machine check (MSCOD = 0x68) observed when memory channel fails to train
22.[Hsd-ES]:[5388337] Against the DIMM rule with 2DPC RDIMM (SR is in DIMM0, DR is in DIMM 1), this channel will be disabled as design, but the system will hang when booting Windows server 2012 R2
23.[Hsd-ES]:[5388340] Need final resolution for FW-UEFI-Vuln-2019-012 BIOSGuard issue
24.[Hsd-ES]:[5388389] [CLX] [SST-BF] SST-BF Frequency Table in BIOS needs minor adjustment due to last minute CPU SKU definition change
25.[Hsd-ES]:[5388264] PurleySktPkg/MemCpgc: Add software timeout and issue cold reset
26.[Hsd-ES]:[5388324] AEP BIOS - ARS Error Inject updates
27.[Hsd-ES]:[1507355635] CpPcRestrictedPkg/Ipmi: User configuration page is  hidden  after setting BMC KCS to Restricted Mode
28.[Hsd-ES]:[5388313] CLONE from skylake_server: [HPE] AEP DIMM's showing ECR_WDATA_PE (data path poisoned) without error media log created (or WDB UE)
29.[Hsd-ES]:[5388339] CLONE from skylake_server: Firmware Test Suite failures with NVDIMM _NBS & _NCH methods
30.[Hsd-ES]:[1507354875] OOB update caused system be in reboot loop under restricted/Deny all mode
31.[Hsd-ES]:[1607594883] [Purley-R][KCS]FRB-2 triggered on option ROMS under Deny All mode.
32.[Hsd-ES]:[1507337951] Released BIOS bug with AEP in description instead of Optane DCPMM.
33.[Hsd-ES]:[1407979768] Purley BMC KCS Policy Control Modes Implementation.
34.[Hsd-ES]:[1806951266] XmlCliDxe Assert on reboot after creating max number of namespaces in UEFI CLI.
35.[Hsd-ES]:[2207690589] Unreleased product code names and build paths retrievable in capsule files.
36.[Hsd-ES]:[FIV10506] PurleyPcPkg\StitchingPkg:[PC Stitching]Update RSTeSataLeagcy version to 6.1.0.1017 for RP
37.[Hsd-ES]:[11683] PurleyPCPkg/StitchingPkg/Microcode:Integrate Microcode 05000029 for CLX B1
38.[Hsd-ES]:[11682] PurleyPCPkg/StitchingPkg/Microcode:Integrate Microcode 04000029 for CLX B0
39.[Hsd-ES]:[OSS_0011668] PurleyPCPkg/ME/SPS: OSS_0011668_Integrate SPS E5_04_01_04_323_0 to Trunk
40.[Hsd-ES]:[11696] PurleyPcPkg/NvmDimmDriver: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3467 from RP
41.[Hsd-ES]:[2103627012] "Password is set successfully" message show up when press "F10" to save the config after create BMC user account.
42.[Hsd-ES]:[11639] Integrate Microcode 02000060 for SKX H0 from PC-Purley Skylake
43.[Hsd-ES]:[11661] Update Production SINIT 1.7.22
RP release Reference code version: CP_PURLEY_0591_D01.
================================================================================
===============================================================================
                                                        0X.02.0040
================================================================================
1.[Hsd-ES]:[2103625822] Revert"[AEP] 55785.1 -  Invalid Configuration - Mixed NVDIMMs and DCPMMs, Step2 - Intermittent POST 0x32 hang and IERR logging."
2.[Hsd-ES]:[1607211313] CpPcRestrictedPkg\Variable\SmiVariable: Race conditions in VariableInterface() allow arbitrary writes inside of SMRAM
3.[Hsd-ES]:[2103626532] Complex Password setting will change to default setting (disable) after reset SUT
4.[Hsd-ES]:[1507212924] Onboard VGA Always On knob is grey out and display output from add-in video card
5.[Hsd-ES]:[1507223712] "DCPMM Invalid Configuration found" after running UEFI NVRAM variables without any DCPMM installed.
6.[Hsd-ES]:[1507140808] Vulnberabilities CVE-2019-6260 as BMC didn't disable superIO
7.[Hsd-ES]:[2103626444] PurleySktPkg\Me: SUT will reset after udpate BIOS/FD/ME via OFU in Linux
8.[Hsd-ES]:[11619] PurleyPcPkg/NvmDimmDriver: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3463 from RP
9.[Hsd-ES]:[2103626509] PurleyPlatPkg\Override: System cannot boot to recovery mode with some memory population
10.[Hsd-ES]:[2103626021] PurleyPcPkg\StitchingPkg: SUT will halt at 0x99 probably when AEP set to 2LM MM mode
11.[Hsd-ES]:[1507136963] PurleyPcPkg\Roms: [WF0-CLX]FRUSDR/SYSCFG utility stall for quite a long time when dumping FRU content or bios/bmc setting under uefishell with USB31000SA installed.
12.[Hsd-ES]:[11617] PurleyPcPkg/NvmDimmDriver: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3461 from RP
13.[Hsd-ES]:[no_sighting] PurleyPcPkg/Microcode: Update Production BIOSACM 1.7.12
14.[Hsd-ES]:[FIV11589] PurleyPcPkg\StitchingPkg:[PC Stitching]Update RSTeSataEfi version to 6.1.0.1017 align with RP
RP release Reference code version: CP_PURLEY_0586_D08.
================================================================================
                                                        0X.02.0031
================================================================================
1.[Hsd-ES]:[1607277367] Operands in a bitwise operation have different size KW issue
2.[Hsd-ES]:[2103626208] It can enroll CA cert via Setup UI after login as user.
3.[Hsd-ES]:[1507072526] ServerAmiRestrictedPkg : FW-UEFI-Vuln-2019-009 UsbRt SMM callout code execution Server Board S2600ST
4.[Hsd-ES]:[1607136428] Include Infineon TPM Driver in Purley-R source tree.
5.[Hsd-ES]:[2103625317] [STP_CLX-R]  RAID option ROM have no display background color and only display character in SOL session.
6.[Hsd-ES]:[2103626238] Stop bits should be "0" according to new ACPI SPCR spec.
7.[Hsd-ES]:[1507136963] [WF0-CLX]FRUSDR/SYSCFG utility stall for quite a long time when dumping FRU content or bios/bmc setting under uefishell with USB31000SA installed.
8.[Hsd-ES]:[2103625234] There are some issue when SUT boot with invalid DCPMM config
9.[Hsd-ES]:[1507036525] CpPcRestrictedPkg\override\MdeModulePkg: There are 7 PSIRT BIOS security issues reported on R15 code base.
10.[Hsd-ES]:[1507173389] SMBIOS type 16/ type 19 show incorrent info.
11.[Hsd-ES]:[1507175341] RSD Type 194 info is incorrect.
12.[Hsd-ES]:[2007797829] BKC Purley-R - BMC Web Console doesn't show CPU and DIMM information.
13.[Hsd-ES]:[1507175309] RSD Type 193 info is incorrect
14.[Hsd-ES]:[2103625822] [AEP] 55785.1 - Invalid Configuration - Mixed NVDIMMs and DCPMMs, Step2 - Intermittent POST 0x32 hang and IERR logging.
15.[Hsd-ES]:[no_sighting] PurleyPCPkg/StitchingPkg/Microcode:Integrate AspeedVideo/ASTVBIOS 1.09 from PC-Purley Skylake
16.[Hsd-ES]:[2103624920] BIOS / ME / FD image still can be updated via OOB feature when the mismatch type is selected
17.[Hsd-ES]:[2103626488] BNP-CLX]Configure out AEP for CFG1 2-1-1(AEP 256G x 4, and 128GB DIMM x12), appeared 0XFA fatal error after power on Fatal error is thrown when high memory is used with the SKU which does not supports.
18.[Hsd-ES]:[no_sighting] PurleyPcPkg/Microcode: Update Production SINIT 1.7.21
19.[Hsd-ES]:[1607230631] Handle KW Issues in XMLCLI packages.
20.[Hsd-ES]:[11575&11576] PurleyPCPkg/StitchingPkg/Microcode:Integrate Microcode 04000026 for CLX B0 and 05000026 for CLX B1
21.[Hsd-ES]:[1507170024] [2019_WW16][WFP] ipmi set bootdev bios/disk sometimes doesn't work
22.[Hsd-ES]:[11544] PurleyPcPkg/NvmDimmDriver: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3458 from RP
RP release Reference code version: CP_PURLEY_0584_D01.
===============================================================================
                                                        0X.02.0010
================================================================================
1.[Hsd-ES]:[1607116940] Add BIOS options to change different PCIe Uncorrectable Error Severity mapping
2.[Hsd-ES]:[1507072526] FW-UEFI-Vuln-2019-009 UsbRt SMM callout code execution Server Board S2600ST
3.[Hsd-ES]:[1507146548] CCB#2591-Q2'19 To add [Onboard VGA Always On] to support GPGPU usage and expose the option in setup/ITK
4.[Hsd-ES]:[1607184056] Purley-R DSG CCB-2700:  Resolve BMC network problem from LAN disabling under BIOS and MAC address problem
5.[Hsd-ES]:[2103624263] STP Q3'18 SFUP test failed with SUSE12.3 OS that show critical issue for ME in BMC web
6.[Hsd-ES]:[1607118287] [Point Release BIOS] 2587 Enable MAC address for specific add-in cards via SMBIOS RSD extensions
7.[Hsd-ES]:[1607202054] [CLX] [SST-BF] SST-BF identification of High Priority cores broken in VMWare ESXi
8.[Hsd-ES]:[5388335] CLONE from skylake_server: [Google]Bug on PurleySktPkg/Dxe/CrystalRidge/AsmRdRand.S
9.[Hsd-ES]:[2103626179] The SUT will halt at early video with some memory config.
10.[Hsd-ES]:[2207272621] WolfPass: PCI device slot id is not unique
11.[Hsd-ES]:[1607193846] [Purley-Refresh] RAS Sync from RP to PC code 5388301
12.[Hsd-ES]:[5388333] Customer request for removing disabled code that is not working right
13.[Hsd-ES]:[5387777] Update Enhanced Warning Log in Intel Reference Code to 1.6
14.[Hsd-ES]:[no_sighting] Integrate microcode CLX A0 mb750655_03000012 to Trunk
15.[Hsd-ES]:[5388296] CLONE from skylake_server: [RAS] Incorrect DIMM location reported when PS finds UCE
16.[Hsd-ES]:[5388329] [CLX] [SST-BF] SST-BF identification of High Priority cores broken in VMWare ESXi
17.[Hsd-ES]:[5388209] DXE_ASSERT - Protocol 'gEfiVariableWriteArchProtocolGuid' is not available
18.[Hsd-ES]:[5347308] [Purley-R][ IFWI 2019.15.3]Post code hang d5 after enable BIOS Gard option in BIOS setup
19.[Hsd-ES]:[5388298] [CLX] [AMI IPS] Dimm re-training and ADR enable results in loosing DIMM data
20.[Hsd-ES]:[1607113667] Purley-R DSG CCB-2570-Complex BMC Password
21.[Hsd-ES]:[1506985873] BNP BdsUpdateHookBuchananPass driver is loaded on Walker Pass.
22.[Hsd-ES]:[1607042642] IIO config help string override by SDP.
23.[Hsd-ES]:[5388322] CLONE from skylake_server: BIOS hangs at "Pipe Exit starting..." message during S3 flow in 2DPC system configuration  
24.[Hsd-ES]:[FIV11501] Integrate true version of NMPTU binary for SPS E5_04.01.04.296.0 to Trunk
25.[Hsd-ES]:[1506764211] [Purley_Refresh]there is no unsigned capsule file generation with daily build
26.[Hsd-ES]:[1607085596] Restrict Update Nvram support for DC requirement
27.[Hsd-ES]:[1607201873] Sync the Setup options value with respect to Purley-R and Purley Sustaining project trunk
28.[Hsd-ES]:[1507108474] BIOS post fail with S2600BPS SKU in Riser solt2 M.2 NVME
===============================================================================
                                                        0X.02.0001
================================================================================
1.[Hsd-ES]:[1607172379] Purley-R DSG CCB-2659: [Q2'19 BIOS]Support for Priority Based Frequency
2.[Hsd-ES]:[11482&11483] PurleyPCPkg/StitchingPkg/Microcode:Integrate Microcode 04000024 for CLX B0 and 05000024 for CLX B1
3.[Hsd-ES]:[1507095678] On 1 CPU system SMBIOS type 9 Current Usage value for CPU 2 - PCIE slot don't follow SMBIOS SPEC.
4.[Hsd-ES]:[11486] PurleyPCPkg/StitchingPkg/Microcode:Integrate Microcode 0200005e for SKX H0 from PC-Purley Skylake
5.[Hsd-ES]:[11490] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3455 from RP
6.[Hsd-ES]:[OSS_0011501]_Integrate SPS E5_04_01_04_296_0 to Trunk
7.[Hsd-ES]:[ 2103625234] There are some issue when SUT boot with invalid DCPMM config
8.[Hsd-ES]:[1607088367] [Purley-Refresh] RAS Sync from RP to PC code 5388214, 5388159, 5387963, 5387936, 5387668
9.[Hsd-ES]:[1507113812] [Carmel Bay] Memory information is not correct under CentOS OS
10.[Hsd-ES]:[no_sighting] Request for inclusion of OPA UEFI 1.9.2.0.0 in Purley BIOS
11.[Hsd-ES]:[5388283] Dynamic loops accessing one element beyond boundary (MAX_TT_ROW) due to <= operator in DimmTT
12.[Hsd-ES]:[5388046] [CLX-AP PO] System getting stuck at postcode FF during AC cycling"
13.[Hsd-ES]:[1607088366] [Purley-Refresh] RAS Sync from RP to PC code 5388037
14.[Hsd-ES]:[1606904999][Purley-Refresh] RAS Sync from RP to PC code 5387239
15.[Hsd-ES]:[5388139] BMC version is changing to NA in bios setup menu after flashing IFWI/ loading any config file
16.[Hsd-ES]:[5388153] CLONE from skylake_server: When running MRC cycling with Apache Pass, each boot results in surprise clock stop.
17.[Hsd-ES]:[5388031] BIOS hang at "Config TDP Level 2..." after enable "Opportunistic SR" with full memory configuration
18.[Hsd-ES]:[5388222] [CLX] Speed Select Base Config P1 frequency is lost and not available to discover when CPU is in a different ISS config than base
19.[Hsd-ES]:[5388195] MRC: Limit EKVCMD Vref high side boundary to 63
20.[Hsd-ES]:[5388301] CLONE from skylake_server: [CR Dungeon] ASSERT_EFI_ERROR 451 while running MLC at high temp
21.[Hsd-ES]:[5388286] [CLX B0] Add datecode check for CTLE for Samsung C-die and D-die
22.[Hsd-ES]:[5388285] [CLX B0] Fatal error during DRAM Rx Eq training on Samsung 8Gb based DIMMs
23.[Hsd-ES]:[5388261] SMBIOS Type 19 for UMA should expose LMMIO gap.
24.[Hsd-ES]:[5388266] FW-UEFI-Vuln-2019-012 Intel BIOS Guard implementation IO TRAP SMI call-out
25.[Hsd-ES]:[5388288] CLONE from skylake_server: We are observing a surprise clock stop after S3 reset
26.[Hsd-ES]:[5388239] DXE_ASSERT when flushing ADWB memory
27.[Hsd-ES]:[5388281] Incorrect DIMM location reported in ADWB or 2LM when injecting CE or UCE
28.[Hsd-ES]:[1606927743] To reduce the build time for PurleyPcPkg.
29.[Hsd-ES]:[no_sighting] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3453 from RP
30.[Hsd-ES]:[5388290] CLONE SKX Sighting: [promoted] Google fixed counter RDPMC failures
31.[Hsd-ES]:[5388101] Add PPR
32.[Hsd-ES]:[No_Sighting] Request for inclusion of OPA UEFI 1.9.2.0.0 in Purley BIOS
33.[Hsd-ES]:[5388231] CPU string is not matched between BIOS and DCL SPEC
34.[Hsd-ES]:[5388284] The current BIOS implemenation is not following the POR validation matrix
35.[Hsd-ES]:[5388260] Intel MRC change broken customrefreshrate setting to 2x refresh.
36.[Hsd-ES]:[5388217] Fix size check for ADDDC Ranks
37.[Hsd-ES]:[5387999] Unnecessary HECI resets causing SPS failures
38.[Hsd-ES]:[1606927743] to reduce the build time for PurleyPcPkg
39.[Hsd-ES]:[5388108] [CLX-AP] Observing Package cstate & Core cstate value of PKG-C1 to be greater than 90% instead of PKG-C6 values.
40.[Hsd-ES]:[5388209] DXE_ASSERT - Protocol 'gEfiVariableWriteArchProtocolGuid' is not available
41.[Hsd-ES]:[5388273] SKU Limit Detection and Error handling
42.[Hsd-ES]:[5388237] AEP FIS version as part of input structure fed to 'Identify DIMM' AEP command is wrong.
43.[Hsd-ES]:[5388229] [MRC] The starting/initial values for CLK signals seems exist problem on Purley-R BIOS
44.[Hsd-ES]:[5388274] Mixed Mode AEP is not throwing out an unsupported warning message
45.[Hsd-ES]:[5388271] PCD Error Handling - BIOS runs into infinite loop on invalid signature
46.[Hsd-ES]:[5388254] LSS - All AEPs Reports Dirty Shutdown After Same-Level BIOS Flash Following a Cold Reset
47.[Hsd-ES]:[5388251] [clone] Purley BIOS HSD 5386983 Implement workaround for CoreBo credit leak issue dropped from SKX/CLX code
48.[Hsd-ES]:[5388178] BIOS don't follow FIS 1.14 to parsing BSR in serial debug msg
49.[Hsd-ES]:[5388261] Fix for SMBIOS Type 19 missing if NUMA disabled
50.[Hsd-ES]:[1507042968] Remove the lock feature of Power LED
51.[Hsd-ES]:[no_sighting] iafw-purley/Purley Refresh:checkout Commit46e9071f1cc1e163c7f6922011f3e8cc2f4d3fea SPS E5_04.01.04.260.0 folder form Trunk
52.[Hsd-ES]:[FIV11400] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3449 from RP
53.[Hsd-ES]:[no_sighting] Change Simics script file EP_DDR4_LBG_MIN.simics memory configuration from 4G to 8G
54.[Hsd-ES]:[FIV_11363] Integrate SPS E5_04.03.03.258.0 to Trunk (CLX AP)
55.[Hsd-ES]:[5388198] L3 Cache Size  is incorrect in SMBIOS table type 7
56.[Hsd-ES]:[5388190] [CLX - AP] Platform is not booting after changing the boot mode to power optimized in Bios setup menu.
57.[Hsd-ES]:[5388252] DCPMM Protocol - do not switch to SMM for TSOD polling state retrieval
58.[Hsd-ES]:[5388198] L3 Cache Size  is incorrect in SMBIOS table type 7
59.[Hsd-ES]:[FIV_11375] Integrate CLX B0 mbf50656_04000022 and CLX B1 mbf50657_05000022
60.[Hsd-ES]:[1507112776]Sync Up the Microcode 0x21 to fix the boot failure issue
61.[Hsd-ES]:[1507094928]Support RSD SMBIOS table 190 NIC
62.[Hsd-ES]:[5387952] PurleyRpPkg: Increase MICROCODE_FV region size in FDF for POC
63.[Hsd-ES]:[5388202] [CR] Update NvmCtlrGetPlatformInterpretedLss & NvmCtlrGetPlatformInterpretedUnlatchedDsc to return new dirty shutdown reasons from BSR
64.[Hsd-ES]:[5388241] CCB 136659 Disable DDRT on SKX CPUs before AEP goes to production
65.[Hsd-ES]:[5388246] [CLX] CPC Error on windows after enabling Prioritized base frequency support
66.[Hsd-ES]:[2103625514] PurleyPcPkg/Restricted: There is no "Direct To Core (D2C)"  and "Direct To UPI (D2K)" option on BIOS Setup and ITK.
RP release Reference code version: CP_PURLEY_0582_D09.
This release is mapping to RP daily build:CP_PURLEY_0582_D19.
================================================================================
                                                        0D.01.0438
================================================================================
1.Remove [Hsd-ES]:[5387873] SMBIOS Type 19/20 is not showing effective memory Size.
2.[Hsd-ES]:[2007793994] BIOS displays 2934 MHz for Current memory Speed instead of 2933MHz.
3.[Hsd-ES]:[1507073575] Patch 2 Die as One to get logic socket ID for CLX-AP
4.[Hsd-ES]:[5388203]CLONE from skylake_server: [IPS 2206782286] AEP surprise warmreset detection does not work
5.[Hsd-ES]:[5387983][CLX-AP] UEFI PXE Boot is not present in the DragonRock BIOS
6.[Hsd-ES]:[5387156] Add support to report FRU information in Error Logs based on CLX-AP 2 dice in 1 Skt
7.[Hsd-ES]:[5388125] [google] BIOS BDAT crc incorrect
8.[Hsd-ES]:[5388163] BIOS hangs during platform boot when get PCD for partition 0 (or 1) fails as a consequence of UCC (or poison)
9.[Hsd-ES]:[5388216] CLONE from skylake_server: [RAS] Clear Poison while ARS running
10.[Hsd-ES]:[5388215] [CLX - AP] Remove 2die as 1S Setup Option
11.[Hsd-ES]:[1507099817] [WFP CLX] IPS Case 00423695 - BIOS does not have a memory setting for 2666 or 2933 memory 
RP release Reference code version: CP_PURLEY_0581_D01.
This release is mapping to RP daily build:CP_PURLEY_0581_D05.
===============================================================================
                                                        02.01.0008
================================================================================
1."System Memory Poison" is renamed as "Enhanced Error Containment Mode" like Purley DSG sustaining. This option is moved from Advanced->System Event Log(hidden in BIOS Setup) to Advanced->Processor Configuration setup page and default value is disabled as like Purley DSG sustaining BIOS.
2.[Hsd-ES]:[1507112201] Default option for Resume on Power Loss changed to 'power on'
3.[Hsd-ES]:[1607077352] Default option for Console Redirection changed to 'Serial Port A'
4.Disable "UpdateNvram" in BIOS so that UpdateNvram can't be used in flash utility like iflash32.
5.[Hsd-ES]:[1507108474] BIOS post fail with S2600BPS SKU in Riser solt2 M.2 NVME
RP release Reference code version: CP_PURLEY_0573_D10.
This release is mapping to RP daily build:CP_PURLEY_0574_D07.
================================================================================
                                                        0D.01.0430
================================================================================
1.[Hsd-ES]:[5388179] CLONE from skylake_server: BKC BIOS maps DCPMM AD memory regions to wrong NUMA nodes when SNC is enabled.
2.[Hsd-ES]:[5388228] DCPMM protocol - OEM SMBus control not released when SMBus acquisition failed
3.[Hsd-ES]:[5388214] CLONE from skylake_server: [HPE] AEP DIMM's showing ECR_WDATA_PE (data path poisoned) without error media log created (or WDB UE)
    
4.[Hsd-ES]:[FIV11127] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3446 from RP
5.[Hsd-ES]:[5388185] Unexpected reset with MCA Recovery Flow in 2LM (eMCA Gen2)
6.[Hsd-ES]:[2103621951] There have some BIOS UI related issue compare with EPS1.07.
7.[Hsd-ES]:[1607033590] [WKP] Getting wrong OEM table ID in ACPI tables
8.[Hsd-ES]:[5388204] Allow microcode updates in knobfile
9.[Hsd-ES]:[5388207] Fix PCD SerializationWaEn flow
10.[Hsd-ES]:[2206776195] NIC on-board is not detected in Bios option on boot manager menu.
11.[Hsd-ES]:[5388210] OpenSSL update to 1.1.0j
RP release Reference code version: CP_PURLEY_0580_D04.
This release is mapping to RP daily build:CP_PURLEY_0580_D07.
===============================================================================
                                                        0D.01.0423
================================================================================
1.[Hsd-ES]:[5388201]CLONE from skylake_server: [Lenovo] System reboot during pipesync in 4S ring with AEP installed
2.[Hsd-ES]:[FIV110055] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3444 from RP
3.[Hsd-ES]:[1607041065] Need to sync the SMBUS Recovery working flow as like NC in PCSD.
RP release Reference code version: CP_PURLEY_0579_D06.
This release is mapping to RP daily build:CP_PURLEY_0579_D09.
===============================================================================
                                                        0D.01.0416
================================================================================
1.[Hsd-ES]:[1607019430]Fix L2 Cache Size Calculation
2.[Hsd-ES]:[10957&10958]Integrate Microcode 04000021 for CLX B0 and 05000021 for CLX B1
3.[Hsd-ES]:[5388112]MSR 4Eh (PPIN_CTL) is not locked on S3 resume
4.[Hsd-ES]:[5388194]From server_sw_fw_nvm.bug: [CR 1.0] Lighting Ridge reboots while injecting large amount of errors
5.[Hsd-ES]:[FIV10935][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3440 from RP   
6.[Hsd-ES]:[5388088]CLX-AP code enabling in IP clean tree
7.[Hsd-ES]:[5388200][DELL] ArsOnBoot causing AEP FW UPdate via FMP to fail
8.[Hsd-ES]:[5388193]SMBIOS protocol requires 2 zero bytes behind SMBIOS recoded being added.
9.[Hsd-ES]:[5388189]CLONE from skylake_server: [Dell] Unsafe shutdown seen with WW06 BKC10
10.[Hsd-ES]:[1507060634]Update ACP BoardName to AcadiaPar
11.[Hsd-ES]:[1507062850]Add SMC Redfish Host Interface(SMBIOS Type 42 for Redfish)
12.[Hsd-ES]:[1507004630]DIMM inforamtion page in BIOS setup can't display full DIMM list with 48 DIMM installed
13.[Hsd-ES]:[1807047308]ARS on Boot Setup Option is missing.
14.[Hsd-ES]:[5388172][CLX] t_cs_oe Jedec spec timing violation on latest bios
15.[Hsd-ES]:[5388181]CLONE from skylake_server: [CR Dungeon][BDC] Systems with 16Gb Dimms failed to boot with Bios 576.D20
16.[Hsd-ES]:[5388144]Need new Panic Refresh and High Watermark settings for 16Gb DIMMs to enable POR in MRC
17.[Hsd-ES]:[2206349991]WalkerPass: U.2 Hot swapping.
18.[Hsd-ES]:[5388144]Need new Panic Refresh and High Watermark settings for 16Gb DIMMs to enable POR in MRC.
19.[Hsd-ES]:[1507062477]WalkerPass: NM_Domain_Limiting_Scope test failed(fail rate:12/120).
20.[Hsd-ES]:[10823&10824]Integrate Microcode 0400001d for CLX B0 and 0500001d for CLX B1
21.[Hsd-ES]:[FIV10839][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3436 from RP.
22.[Hsd-ES]:[FIV10839]Integrate IntelDCPersistentMemoryDriver_v01.00.00.3436 to Trunk.
23.[Hsd-ES]:[No Sighting][PC Stitching]Update RSTeSataEfi version to 6.0.0.1024 for WalkerPass.
24.[Hsd-ES]:[5388161]2LM ERROR message in serial log with DDR4 memory only configuration.
25.[Hsd-ES]:[5388184]From server_sw_fw_nvm.bug: DXE_ASSERT during cold boot after performing an uc error for WLM transaction type.
26.[Hsd-ES]:[5388146]"NGN Factory Reset/clear" option enabling does not change the "Average Power Budget" to its default factory value (15W).
27.[Hsd-ES]:[FIV10506]Update RSTeSataEfi version to 6.0.0.1024 to CLX_AP and TPP binary.
28.[Hsd-ES]:[no_sighting]Integrate CLX B0 mbf50656_0400001d and CLX B1 mbf50657_0500001d
29.[Hsd-ES]:[No Sighting]Update NVMDIMMdriver and NVMDIMMHii to v01.00.00.3429 on Walker Pass.
30.[Hsd-ES]:[5388179]CLONE from skylake_server: BKC BIOS maps DCPMM AD memory regions to wrong NUMA nodes when SNC is enabled.
31.[Hsd-ES]:[1507055171]Implement RSD SMBIOS table type 192, 194, 200.
32.[Hsd-ES]:[1507002208]Adjust UPI TXEQ parameters for AcadiaPark and BiscaynePark board.
33.[Hsd-ES]:[5388177][Purley-R][2S] [IFWI: 2019.07.4.06.0312_CRB] system will hang when boot with 576_D17 BIOS
34.[Hsd-ES]:[1507040915]WalkerPass: Active Processor Cores option is not be available in Bios Setup.
35.[Hsd-ES]:[FIV10713][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3429 from RP
36.[Hsd-ES]:[5388173][Purley-R][CR-2S] [IFWI:2019.07.3.05.0228_CRB] Redundant information pops up after system entering UEFI Shell
37.[Hsd-ES]:[5388169]MRC: Remove D_RST_MASK_FNV_D_UNIT_0_REG and DA_DDRT_TRAINING_RC0F_FNV_DA_UNIT_0_REG  from BIOS programming flow
38.[Hsd-ES]:[5388129][CLX-AP][WW04][IFWI: 572.D02] L2 cache size is incorrect in BIOS when enable the 2 die in 1 socket
39.[Hsd-ES]:[FIV10680][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3425 from RP
40.[Hsd-ES]:[5388042][Lenovo] PCU_NOT_RESPONDING FatalError happened because no enough time to wait PCU
41.[Hsd-ES]:[5388160]SingleSmi for UCE
10.[Hsd-ES]:[5388144]Need new Panic Refresh and High Watermark settings for 16Gb DIMMs to enable POR in MRC
42.[Hsd-ES]:[5388159]CLONE from skylake_server: [CR Dungeon] RetrieveEventDataFromAllDimms: BSP+AP execution exceeded 1s - Kernel Panic
43.[Hsd-ES]:[5388162]CLONE from skylake_server: [Lenovo] ARS setting for different OS
44.[Hsd-ES]:[[no_sighting]Integrate Microcode 01000148 for SKX B1 on TPP
45.[Hsd-ES]:[10611] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3420 from RP
46.[Hsd-ES]:[OSS_0010610] Integrate SPS E5_04_01_04_256_0 to Trunk
47.[Hsd-ES]:[5388154]CLONE from skylake_server: [ggogle] 3DS 8Rx4 LRDIMM high training failure rate after 2018WW46 BKC
48.[Hsd-ES]:[5388158]CCB 136662 Extend Command Access Policy to lock specific mailboxes
49.[Hsd-ES]:[5388122]system does not throw fatal error or halts when booted without a DDR4 and with only DCPMM
50.[Hsd-ES]:[1606953974]Help String Displayed Incorrectly.
51.[Hsd-ES]:[5388133][SMBIOS] Sum of Type19 size exceeds real memory size - exclude non memory area from 4 GiB legacy SAD
52.[Hsd-ES]:[5388150]Debug print show memory disabled and EWL log with WW04 BKC
53.[Hsd-ES]:[588825][Oracle] CR Assert Threads not in sync in SMM
54.[Hsd-ES]:[5388135]CLONE from skylake_server: [HPE]Endless Reboot when Apache Pass Dimms are Mapped Out
55.[Hsd-ES]:[FIV10599]Integrate IntelDCPersistentMemoryDriver_v01.00.00.3418 to Trunk
56.[Hsd-ES]:[5388132]CLONE SKX Sighting: [2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2 - add BIOS knob to disab
57.[Hsd-ES]:[5388103][Purley-R][4S] SUT can't  boot up when CPU installed on discrete CPU socket number
RP release Reference code version: CP_PURLEY_0578_D07.
This release is mapping to RP daily build:CP_PURLEY_0579_D03.
================================================================================
                                                        02.01.0007
================================================================================
1.[Hsd-ES]:[no_sighting] Purley Refresh OpenSSL version update to 1.1.0j.
RP release Reference code version: CP_PURLEY_0573_D10.
This release is mapping to RP daily build:CP_PURLEY_0574_D07.
================================================================================
                                                        02.01.0006
================================================================================
1.[Hsd-ES]:[2103625393] [STP-R] [R0003] TPM BitLocker (Boot order change) test result does NOT match expected result.
2.Remove [Hsd-ES]:[5387873] SMBIOS Type 19/20 is not showing effective memory Size.
RP release Reference code version: CP_PURLEY_0573_D10.
This release is mapping to RP daily build:CP_PURLEY_0574_D07.
================================================================================

                                                        02.01.0003
================================================================================
1.Rename BIOS ID from D0374 to R0003
================================================================================

                                                         0D.01.0374
================================================================================
1.[Hsd-ES]:[5388103] [Purley-R][4S] SUT can't  boot up when CPU installed on discrete CPU socket number.
2.[Hsd-ES]:[2103625255] PXE boot entry still list in Boot Manager when set NIC port to Disabled.
3.[Hsd-ES]:[1606886827] [Sysinfo]Few BIOS read only variables have unknown value in sysinfo_log file while using CLX-R CPU.
4.[Hsd-ES]:[2206185624] Fix Capsule Integrity Check.
5.[Hsd-ES]:[FIV10506] [PC Stitching]Update RSTeSataEfi version to 6.0.0.1024 for RP.
6.[Hsd-ES]:[10536] Integrate Microcode 0200005a for SKX H0 from PC-Purley Skylake.
7.[Hsd-ES]:[1507035968] Add 3 memory options to support 2933 2DPC on ACP.
8.[Hsd-ES]:[5388113] [CLX-AP] BIOS Locks up when SNC 1 way is turned on.
9.[Hsd-ES]:[1606947029] Remove the integrated Infineon TPM module as it does not follow security requirement.
10.[Hsd-ES]:[2206529825] Add Warnings displayed prior to OS boot if DCPMMs on CPU socket are not partitioned identically (mismatched capacity size).
11.[Hsd-ES]:[1507040597] There is a new fail module when run chipsec_main.py with BIOS 0D010348.
12.[Hsd-ES]:[no_sighting] Purley Refresh BIOSID Update to 574.
13.[Hsd-ES]:[1507016191] CPU HP SMBUS to SMC has no functionality.
14.[Hsd-ES]:[OSS_0010512] Update Production SINIT 1.7.2.
15.[Hsd-ES]:[10537&10538] Integrate Microcode 0400001c for CLX B0 and 0500001c for CLX B1.
16.[Hsd-ES]:[5388134] System halts with IPC BIOS at PC 36 (both RP and PCSD ) - release blocker.
17.[Hsd-ES]:[1408831622] It should not be possible to enable IODC on 1S 1die topologies.
18.[Hsd-ES]:[5388132] CLONE SKX Sighting:[2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2 - add BIOS knob to disable WA.
19.[Hsd-ES]:[5388061] Intel RC code generates unwanted warnings of NVDIMM configuration.
20.[Hsd-ES]:[5388078] Read/WriteFnvCfg default case for an unknown interface type should default to something safe instead of causing a fatal error.
21.[Hsd-ES]:[no_sighting] Integrate CLX B0 mbf50656_0400001c and CLX B1 mbf50657_0500001c.
22.[Hsd-ES]:[no_sighting] Integrate SKX H0 signed patch mb750654_0200005a on all builds.
23.[Hsd-ES]:[10534] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3413 from RP.
24.[Hsd-ES]:[FIV10534] Integrate IntelDCPersistentMemoryDriver_v01.00.00.3413 to Trunk.
25.[Hsd-ES]:[1606940387] Suppressing Setup Knobs as required for DC Candidate.
26.[Hsd-ES]:[5388099] Unable to disable Top-swap bit with Top-Swap jumper.
27.[Hsd-ES]:[5388041] Few DIMMs fail to boot @2400.
28.[Hsd-ES]:[5387705] [Gigabyte/Lenovo]Fast Cold Boot will make system hang at 0xEE if AEP(AD mode ONLY) + 3DS RDIMM.
29.[Hsd-ES]:[5388112] MSR 4Eh (PPIN_CTL) is not locked on S3 resume.
30.[Hsd-ES]:[2206185624] BIOS Capsule Update Integrity Bypass.
31.[Hsd-ES]:[1507040003] HSTI function check show "HSTI validation failed".
32.[Hsd-ES]:[FIV_10506] Update RSTeSataEfi version to 6.0.0.1024.
33.[Hsd-ES]:[FIV_10512] Integrate SINIT 1.7.2 PW.
34.[Hsd-ES]:[5388042] [Lenovo] PCU_NOT_RESPONDING FatalError happened because no enough time to wait PCU.
35.[Hsd-ES]:[5388090] MRC to handle invalid interleaving
36.[Hsd-ES]:[no signting] Purleyiafw-purley/Purley Refresh: Change SKX H0 0x59 patch to 0x57 patch
37.[Hsd-ES]:[10470] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3410 from RP
38.[Hsd-ES]:[1507008591] HW Validation page should be hidden option in BIOS setup.
39.[Hsd-ES]:[1507032707] PurleyPlatPkg/BmcSmbiosTables: Fix SMBIOS Type 193 MP Assertion on ACP
40.[Hsd-ES]:[1506998520] PurleyPcPkg\Restricted: PCIe Bifurcation of CPU1 Die1 IOU1 and IOU2 are x4x4x4x4
41.[Hsd-ES]:[5388063] CLONE from skylake_server: [CR Dungeon] ASSERT_EFI_ERROR 451 while running MLC at high temp
42.[Hsd-ES]:[FIV10431] Integrate SKX H0 debug patch mb750654_8200005a
43.[Hsd-ES]:[no signting] Integrate CLX B0 debug patch mbf50656_8400001a
                          Integrate CLX B1 debug patch mbf50657_8500001a
44.[Hsd-ES]:[10420] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3405 from RP
45.[Hsd-ES]:[5387873] SMBIOS Type 19/20 is not showing effective memory Size
46.[Hsd-ES]:[5387994] CLONE SKX Sighting: [2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2
47.[Hsd-ES]:[5388083] [2019_WW02][BIOS:0568D10][Lightning Ridge][P&P] MLC remote idle latency is 165ns,much higher than target 140.5ns.
48.[Hsd-ES]:[5388106] [CR] Out of Resources after injecting media temperature error
RP release Reference code version: CP_PURLEY_0573_D10.
This release is mapping to RP daily build:CP_PURLEY_0574_D07.
================================================================================
                                                      0D.01.0348
================================================================================
1.[Hsd-ES]:[2103624617] The BMC password can set less than 6 characters in BIOS setup menu
2.[Hsd-ES]:[1606841765] AEP invalid config with WFP BIOS for supporting factory\INT team\Dungeon team
3.[Hsd-ES]:[OSS_0010347]Integrate Microcode 04000017 for CLX B0 from PC-Purley Skylake
      
           [OSS_0010348]Integrate Microcode 05000017 for CLX B1 from PC-Purley Skylake
4.[Hsd-ES]:[2103624462] The SEL description display abnormal after use wrong BIOS password via EWS BMC OOB
5.[Hsd-ES]:[FIV_10379] Re-Integrate SPS E5_04.03.02.253.0 to Trunk (CLX AP/DRK) which includes BIN/ROM files
6.[Hsd-ES]:[no_sighting] Integrate CLX B0 and B1 patch 0x17 to master branch
7.[Hsd-ES]:[5387979] [HPE] HPRTO  wipes Thermal logs
8.[Hsd-ES]:[1507022107]To Replace BIOS Splash Screen to meet new marketing requirement
9.[Hsd-ES]:[2103625047] [STP_OOB update]  there is checked failure in password  event Asserted after enable 'Enforced Password Support and reboot system
10.[Hsd-ES]:[1606916011] Missing BIOS option DMI-PCIe Port MPSWorkaround.
11.[Hsd-ES]:[1408817460] KTI uniphy recipe update for CLX-AP
12.[Hsd-ES]:[5388032] PurleyRestrictedPkg/StitchingPkg: [CLX-AP] After upgrading SPS image from E5_04.01.02.200.0 to E5_04.01.03.239.0, stitching hangs during BIOS build
13.[Hsd-ES]:[OSS_0010536]Integrate SPS E5_04_01_04_251_0 to Trunk
14.[Hsd-ES]:[FIV10351][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3402 from RP
15.[Hsd-ES]:[OSS_0010349]Integrate Microcode 04000019 for CLX B0 from PC-Purley Skylake
                                      
16.[Hsd-ES]:[OSS_0010350]Integrate Microcode 05000019 for CLX B1 from PC-Purley Skylake
17.[Hsd-ES]:[5388044]CLONE from skylake_server: [HPE] Mailbox accesses from DSM need to be throttled
18.[Hsd-ES]:[5388077]Purely BIOS is locking the RAPL MSR and breaking legacy usage models
19.[Hsd-ES]:[5388086]CLX: PBF High Priority Core List requires slight modification
20.[Hsd-ES]:[5388068] imc sysfeatures1 register incorrectly initialized in single thread MRC mode
21.[Hsd-ES]:[5388030] [CLX AP] BIOS went into infinite loop of booting when PCI i/o and MMIO resource allocation failure happened
    
22.[Hsd-ES]:[5387906] [IPS 2203744674] Prevent loading VROC and VMD when VMD is disabled.
23.[Hsd-ES]:[5387519] [CLX-AP] 2 die in 1 support - With code isolation from CLX-SP
24.[Hsd-ES]:[5388053] Average Power Budget incorrect value
25.[Hsd-ES]:[5388085] CLONE from skylake_server: Need BIOS to change Clear History knob to non-DFX
26.[Hsd-ES]:[1506864596] Updated smbios information for WalkerPass.
27.[Hsd-ES]:[1507017311] SFID value is wrong with web post bios
28.[Hsd-ES]:[5387674]CCB 136607 need BIOS to switch to SMbus when DDRT fails for debug data collection & recovery
RP release Reference code version: CP_PURLEY_0571_D03.
This release is mapping to RP daily build:CP_PURLEY_0572_D04.
================================================================================
                                                      0D.01.0338
================================================================================
1.[Hsd-ES]:[1506129880] PurleyPcPkg\Uba: UPI latency performance parameters which impact bandwidth and latency to be exposed in setup/ITK/syscfg
2.[Hsd-ES]:[2006669546] RAID module RMS3HC080 and Software RAID RSTe can't work together on a Wolf Pass system.
3.[Hsd-ES]:[5388058] Graceful handling of invalid memory configurations (two NVDIMMs in one channel)
4.[Hsd-ES]:[5388034] [CR] Non-functional DIMMs after PCD corruption
5.[Hsd-ES]:[1507016873] SUT will hang and can't boot to windows OS.
6.[Hsd-ES]:[1504582491]CCB 2022: MSFT Azure Stack requires Support storage and networking SMBIOS extensions for RSD2.2 on WFP
7.[Hsd-ES]:[2103617388]PurleyPcPkg\Uba: When hotplug NVMe HDDs the RSTe GUI location couldn't match actual HDDs location
8.[Hsd-ES]:[1506438632]PurleyPcPkg\Platform: SOL function terminal type need to support more terminal types the same as console redirection types
9.[Hsd-ES]:[1606892435]Sync PSIRT-BIOS-2017-025 Untested Memory Not Covered by SMM Protection changes.
10.[Hsd-ES]:1506131214] PurleyPcPkg\Restricted: Add BIOS options in ITK to change USB 2.0 ports equalization parameters
11.[Hsd-ES]:1506132509][BNP ]SUT hang post screen when run DC cycles
12.[Hsd-ES]:[1506132901][BNP LCR]MTT CPU1/MTT CPU2 sensors show no reading when run AC cycles and can't recovery within 300s[Only patch for this issue, not a final solution]    
13.[Hsd-ES]:[2202762181]Warning SEL during AC Cycling: BMC FW Health reports SSB Temp has failed and may not be providing a valid reading.
14.[Hsd-ES]:[2205038517]Random Machine Check failure QPI Phy init abort during reboot reported on S2600ST.
15.[Hsd-ES]:[2103624878]With AIC Card populated in RJ45 MB, return data ˇ°CB?when execute "Get AIC MAC address"
16.[Hsd-ES]:[2103614644][WFP] "HDD Rebuild in progress" events were occurred during DC cycling
    Code sync from Purley sustaining to refresh trunk
17.[Hsd-ES]:[1504579991]WFP IFT config dat support class 3
    Code sync from Purley sustaining to refresh trunk
18.[Hsd-ES]:[1504654004]CpPcRestrictedPkg\SecureBoot: request to modify PCH SATA Tx De-emph and Rx CTLE setting
19.[Hsd-ES]:[150396363]CpPcRestrictedPkg\SecureBoot: BIOS should include production key when secure boot enable-Update the key with OU=Platform Platform BIOS Dev
20.[Hsd-ES]:[1506119814]PurleyPlatPkg\Platform: HSTI is absent on Windows Server 2016
21.[Hsd-ES]:[1506871190]CpPcRestrictedPkg\ITK50: syscfg /bldfs "" not working the same way an F9 in the BIOS setup does
 Sync code change from Skylake_PC_Production tree
22.[Hsd-ES]:[1505084878]CpPcRestrictedPkg\Bds: Sprint: XL710 show the same boot order name in Boot management
23.[Hsd-ES]:[1506861772]CpPcRestrictedPkg\override: NVME UEFI driver should wait for  the correct timeout time as programmed in NVME card's timeout value from NVME spe Sync code change from Skylake_PC_Production tree
24.[Hsd-ES]:[5388072
]PurleySktPkg/Library/ProcMemInit: [[Purley-R][CR_2S][IFWI:2019.01.4.08.2132_CRB]SUT will hang at EE and occur CATER error and restart after set BIOS options.]
25.[Hsd-ES]:[5388061]CLONE from skylake_server: [IPS 2206381747] Intel RC code generates unwanted warnings of NVDIMM configuration.
26.[Hsd-ES]:[5388059]CLONE from skylake_server: [IPS 2206381747] Intel RC code configures DCPMM DIMMs of different sizes across sockets.
27.[Hsd-ES]:[5388008]CLONE from skylake_server: From server_sw_fw_nvm: Changing BIOS Rank Enable BitMask on first controller on selected socket will remove every region on that socket
28.[Hsd-ES]:[5388039] BIOS not padding zeros on DIMM Serial Number
29.[Hsd-ES]:[5388037]PurleySktPkg/MemRas: Invalid address is reported by OS after setting poison under 2LM mode
30.[Hsd-ES]:[5388057]ServerSiliconPkg/PeiPchInitLib [BIOS][LBG] Bios needs to program KRM_CB SAI policy CP to enforce access control to Kerem Phy layer IP
31.[Hsd-ES]:[1505083003] PurleyPlatPkg\Platform: Support more memory vendor DIMMs on Purley
32.[Hsd-ES]:[1504750181] PurleyPcPkg\Uba: SMBIOS type 9 segment group number should be all 0
33.[Hsd-ES]:[1506129887] CpPcRestrictedPkg\Library: Extend option value range for Memory Correctable Error Threshold
34.[Hsd-ES]:[1606841765]AEP invalid config with WFP BIOS for supporting factory\INT team\Dungeon team
35.[Hsd-ES]:[5388056] klocwork cleanup - with tip 567d07.
36.[Hsd-ES]:[2103625014] The copyright should be Copyright (c) 2006-2019 instead of Copyright(c) 2006-2018.
37.[Hsd-ES]:[1606695157] Analyze and Fix KW Issues in Purley PCSD project.
38.[Hsd-ES]:[FIV10305] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3394 from RP
39.[Hsd-ES]:[5388023] Request to update MB (CSR) access flow in BIOS (WA for EKV RTL bug)
40.[Hsd-ES]:[2103622487] 1st boot to DVD drive w/ ESXi6.7 disc will show "Boot failed" msg under uEFI mode
41.[Hsd-ES]:[1504400810] Some information incomplete display at the bottom of BIOS setup main page by sol in linux
42.[Hsd-ES]:[1606695157] Analyze and Fix KW Issues in Purley PCSD project.
43.[Hsd-ES]:[5387674] CCB 136607 need BIOS to switch to SMbus when DDRT fails to debug data collection & recovery
RP release Reference code version: CP_PURLEY_0568_D22.
This release is mapping to RP daily build:CP_PURLEY_0569_D06.
================================================================================
                                                      0D.01.0324
================================================================================
1.[Hsd-ES]:[no_sighting][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3393 from RP
2.[Hsd-ES]:[1506949200]Walkerpass:add VMD support on U.2 SSD
3.[Hsd-ES]:[no_sighting] Integrate Microcode 02000059 for SKX H0 from PC-Purley Skylake
4.[Hsd-ES]:[1506997354]Fix "reset -s" command can't shutdwon system issue
5.[Hsd-ES]:[5388064] CLONE from skylake_server: [HPE] Apache Pass DSM's using SMI interface - Change Default to ASL
6.HSD5387949:Enable D2K on CLX-AP. 
7.HSD5387925: Re-enable D2K on CLX 2S
8.[Hsd-ES]:[1506764211][Purley_Refresh]there is no unsigned capsule file generation with daily build
9.[Hsd-ES]:[5387994] CLONE SKX Sighting: [2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2
10.[Hsd-ES]:[5387990] Adding DcpmmFisProtocol with support for reading ARS status
11.[Hsd-ES]:[5388003] CLONE from skylake_server: [Dell][WW40][QS] One AEP Dimm got mapout in Socket 1, Windows Interleave/Namespace/Disk create from the Socket 0 fail too
12.[Hsd-ES]:[2206426003] Missing BIOS option to set RDT CAT Opportunistic.
13.[Hsd-ES]:[5388035][Purley-R MRC] There's a error cause RMT run fail. (BurstLength value exceeds maximum linear value and is not a power of 2.)
14.[Hsd-ES]:[1506980475]PurleyPcPkg\Ipmi: A coding error in IPMI KCS driver
15.[Hsd-ES]:[1606695157]Analyze and Fix KW Issues in Purley PCSD project.
RP release Reference code version: CP_PURLEY_0568_D10.
This release is mapping to RP daily build:CP_PURLEY_0568_D14.
=================================================================================

                                                        0D.01.0299
================================================================================
1.[Hsd-ES]:[FIV9892][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3382 from RP
2.[Hsd-ES]:[5388020][CLX] BIOS _CPC implementation is broken causing issues with PBF core mapping
3.[Hsd-ES]:[OSS_0010043] Update SINIT 1.7.1 NPW
4.[Hsd-ES]:[5388036] CLONE from skylake_server:  [Dell] PCD Corruption - CR DXE driver changes
5.[Hsd-ES]:[OSS_0010020] Integrate Microcode 05000014 for CLX B1 from PC-Purley Skylake
            
6.[Hsd-ES]:[OSS_0010021] Integrate Microcode 04000014 for CLX B0
7.[Hsd-ES]:[5388006] CCB 136634 Restore DCPMM Secure Erase feature from external release
    
8.[Hsd-ES]:[5388026] CLONE from skylake_server: Enable NvmdimmPowerCyclePolicy by default
9.[Hsd-ES]:[5388004] Override user provided vdd settings when AEP is present on socket
10.[Hsd-ES]:[5388032] [CLX-AP] After upgrading SPS image from E5_04.01.02.200.0 to E5_04.01.03.239.0, stitching hangs during BIOS build
11.[Hsd-ES]:[2103623750] [OOB]BIOS configurations can't be changed via EWS
12.[Hsd-ES]:[FIV10016] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3387 from RP
13.[Hsd-ES]:[5388029] [CLX  B1]Bios bits set incorrectly on HWPM mode
RP release Reference code version: CP_PURLEY_0566_D03.
This release is mapping to RP daily build:CP_PURLEY_0567_D10.
=================================================================================

=================================================================================
                                                        0D.01.0286
================================================================================
1.[Hsd-ES]:[2103623750][OOB]BIOS configurations can't be changed via EWS
2.[Hsd-ES]:[5387994] CLONE SKX Sighting: [2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2   
3.[Hsd-ES]:[5387998] DDR-T POR compatibility warning printed when there is no DDRT in Socket
4.[Hsd-ES]:[5388010] Follow up to presighting 588565: Boot Issues - DXE_ASSERT_CR Protocol
5.[Hsd-ES]:[5387294] SDL300/385 Setup Variable - SDL S3 Analysis-MEMORY-revert the changes.
6.[Hsd-ES]:[5387949] Enable D2K on CLX-AP.
7.[Hsd-ES]:[2103624661] There is no uncorrectable error(ED1=0xA1) in SEL after inject poison error on DCPMM.
8.[Hsd-ES]:[1506983981] Adding new build in IAFW_Purley to support CLX A0 CPU support.
9.[Hsd-ES]:[2103624675] The behavior of processor cores disabled via ipmi and Setup UI is incorrect.
10.[Hsd-ES]:[5388005] CLONE from skylake_server: [google] WW28 - context block failures - SNC reconfig warmreset --> surprise clk stop
    
   
11.[Hsd-ES]:[5387989] CLONE from skylake_server: incorrect TEMP_LO for AEP
   Change AEP TEMP_LO from 84 to 82
12.[Hsd-ES]:[5387294] SDL300/385 Setup Variable - SDL S3 Analysis-MEMORY-revert the changes.
13.[Hsd-ES]:[2103624203] Without AIC Card populated,return data contains onboard NIC info when execute "Get AIC MAC address".
14.[Hsd-ES]:[5387994] CLONE SKX Sighting: [2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2
15.[Hsd-ES]:[5388012] CLONE SKX Sighting: [2LM] 2S Supercollider program section HA Conflcits Heavy fails with data error on CRP05D
16.[Hsd-ES]:[5388013] CLONE SKX Sighting: [1LM AD] 2S 2:2:2 LRDIMM - Supercollider+ SDDC harasser hit 3 strike TO and UFSENT in WPQ
17.[Hsd-ES]:[FIV9892] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3382 from RP
18.[Hsd-ES]:[no_sighting] Integrate CLX B0 debug patch mbf50656_84000014
                       Integrate CLX B1 debug patch mbf50657_85000014
19.[Hsd-ES]:[5388000] MRC CustomRefreshRate feature is violating DRAM spec with 16Gb density DRAMs
20.[Hsd-ES]:[5387994] CLONE SKX Sighting: [2LM] 4S supercollider hang with TOR timeout, 3strike on 2-2-2
21.[Hsd-ES]:[1506972479] [Purley CLX BIOS]Fix debug bios with CR build flag will assert on Acadia Park board issue
RP release Reference code version: CP_PURLEY_0564_D09.
This release is mapping to RP daily build:CP_PURLEY_0565_D07.
=================================================================================
                                                      0D.01.0271
================================================================================
1.[Hsd-ES]:[no_signting] Purley Refresh BIOSID Update to 564
2.[Hsd-ES]:[no_signting] PurleyPCPkg/StitchingPkg/Microcode:Integrate Microcode 04000013 for CLX B0 and 03000010 for CLX A0 from PC-Purley Skylake
3.[Hsd-ES]:[OSS_0009825] Update Production BIOSACM 1.7.1
4.[Hsd-ES]:[OSS_0009507] Integrate SPS E5_04.01.03.239.0 to Trunk
5.[Hsd-ES]:[5387462] PCI Slot Implemented bit mechanism fix
6.[Hsd-ES]:[FIV9771] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3380 from RP
7.[Hsd-ES]:[5387984] Cloned From SKX Si Bug Eco: CLONE SKX Sighting: [1LM AD][CLX VV B0] 4S supercollider + ddrt error flow causes slow progress timeouts/hang when timeouts disabled
8.[Hsd-ES]:[5387981] CLONE from skylake_server: [Dell] PCD Corruption - BIOS changes for recovery flow
9.[Hsd-ES]:[5387985]  System hang when update from WW46 BKC to WW48 BKC
RP release Reference code version: CP_PURLEY_0563_D11.
This release is mapping to RP daily build:CP_PURLEY_0564_D01.
=================================================================================
=================================================================================
                                                      0D.01.0261
================================================================================
1.[Hsd-ES]:[2204324560]Request for Wolfpass BIOS to Enable Lock Chipset and 3StrikeTimer Knobs in Menu.
2.[Hsd-ES]:[2103624392]ISS setting can not be changed on Setup UI after change the setting via ipmi with user mode and RSD mode enabled.
3.[Hsd-ES]:[5387960][CLX B0 VV] 2LM + AD mcnmcachingintl register is set incorrectly
 and breaks ADDDC
4.[Hsd-ES]:[5387964]When erase all dimms with locked state then reset,
SUT will hang in code 0x03.
5.[Hsd-ES]:[2103624321]CPU1 core number display abnormal when change Active processor cores in BIOS setting
6.[Hsd-ES]:[5387089]SR-IOV spec violation
7.[Hsd-ES]:[2103624380]The SMBIOS Type 19 memory size is incorrect with DCPMM 2LM config.
8.[Hsd-ES]:[5387974][CLX] BIOS incorrectly sets CSR_DESIRED_CORES when enabling ISS
9.[Hsd-ES]:[5387552]TC5 to VC mapping fix
10.[Hsd-ES]:[5387969]CLONE from skylake_server: AD region will become unknown after inject software fatal error
11.[Hsd-ES]:[FIV9650]Integrate IntelDCPersistentMemoryDriver_v01.00.00.3374 to Trunk
12.[Hsd-ES]:[2103623219][Purley_refresh] SEL show Uncorrectable Error generate after inject Correctable Error to AEP with 2-1-1 2LM(Independent Mode) config
13.[Hsd-ES]:[5387960][CLX B0 VV] 2LM + AD mcnmcachingintl register is set incorrectly
 and breaks ADDDC
14.[Hsd-ES]:[1506953673]Update B0 PO Changes for ACP and BCP
15.[Hsd-ES]:[2206153642]HOST SMBus needs to be isolated after booting to OS
RP release Reference code version: CP_PURLEY_0562_D10.
This release is mapping to RP daily build:CP_PURLEY_0563_D04.
=================================================================================
                                                      0D.01.0250
================================================================================
1.[Hsd-ES]:[1408463799] Disable Invalid DCPMM Config Check in PCSD BIOS.
2.[Hsd-ES]:[1506766438]To update OOB sensor numbers
3.[Hsd-ES]:[1506948369]WalkerPass: Early video does not work with latest code base.
4.[Hsd-ES]:[5387963] Platform crash and DXE_ASSERT in bios after receiving an interrupt with illegal access (read unimplemented register)
5.[Hsd-ES]:[1806597377]ServerSiliconPkg PeiDxeSmmPchSerialIoLib.c is empty and should be removed from Dsc file
6.[Hsd-ES]:[1506948332]PurleyPcPkg/StitchingPkg: Remove ESRTII from Stitch INI and Setup
7.[Hsd-ES]:[OSS_0009535]Integrate Microcode 02000057 for SKX H0 from PC-Purley Skylake
8.[Hsd-ES]:[OSS_0009507] Integrate SPS E5_04_01_03_237_0 to Trunk
9.[Hsd-ES]:[5387927] CLONE from skylake_server: [HPE] Apache Pass DSM's using SMI interface
10.[Hsd-ES]:[1606806603]Change in PurleyPlatPkg : Moving XmlCliCommon folder inside XmlCliRestricted.
11.[Hsd-ES]:[OSS_0009515/OSS_0009516]PurleyPcPkg/Microcode: Update Production BIOSACM 1.7.0/SINIT 1.7.0
12.[Hsd-ES]:[1408463799]MF support for FactoryResetClear knob
13.[Hsd-ES]:[FIV9519]Update NvmDimmDriver Version to 01.00.00.3373
14.[Hsd-ES]:[5387908]CCB 136618 CLX + AEP Memory Channel Efficiency Improvements
15.[Hsd-ES]:[5387938]SK Hynix-Rambus 16Gb-64GB 2Rx4 RDIMM is failing Late CMD-CLK Training with BIOS 554D03
16.[Hsd-ES]:[5387865]klocwork cleanup - platform (remaining items) Klocwork clean up
17.[Hsd-ES]:[5387947][CLX] [GCC] Mark Basetools files as executable
RP release Reference code version: CP_PURLEY_0561_D09.
This release is mapping to RP daily build:CP_PURLEY_0562_D03.
=============================================================================
                                                     0D.01.0241
================================================================================
1.[Hsd-ES]:[5387955]when Factory reset/clear history is enabled, AvgPowerBudget should be 15W setting
2.[Hsd-ES]:[5387954]MP4 3DS RDIMM 1DPC logging TOR TO running rankSpare
3.[Hsd-ES]:[5387865]klocwork cleanup - platform (remaining items) Klocwork clean up
4.[Hsd-ES]:[5387804][JedecNvDimm] About Code Change #5386631 might cause NULL point operation.
5.[Hsd-ES]:[2103623925]System cannot boot into Suse 12 sp3 OS when OS is install in the hard drive connect via RMS3HC080 and add-in "intel_iommu=on" in grub file
6.[Hsd-ES]:[2103624203]Without AIC Card populated, return data contains onboard NIC info when execute  "Get AIC MAC address".
7.[Hsd-ES]:[5387936]CLONE from skylake_server: From server_sw_fw_nvm: No ACPI notification occurs in case of errors found by patrol scrubber
8.[Hsd-ES]:[1506936333]CpPcRestrictedPkg/CommonSetupLib:Create default ThermalSetup
9.[Hsd-ES]:[2007579425]Ngn Lock knob added for CLX PCSD
10.[Hsd-ES]:[2204077884]WFP server SUP R0013 hangs on first boot after memory configuration changed.
11.[Hsd-ES]:[2205563452](CLX-B0) To confirm if AD/2LM snoopy mode features are implemented
12.[Hsd-ES]:[5387519]HT disable boot issue after 2 die in 1 change
13.[Hsd-ES]:[1506111824]PurleyPcPkg: Update WKP pcie port configurations.
14.[Hsd-ES]:[1506941312]PurleyPcPkg\StitchingPkg: Walker Pass: Remove ESRTII oprom support from FDF and stitching config.
15.[Hsd-ES]:[1506757776]PurleyPcPkg/Restricted: Dual video enhancement.
16.[Hsd-ES]:[OSS_0009094]Integrate SPS E5_04_01_03_236_0 to Trunk
17.[Hsd-ES]:[5355128]TOR timeout during ADDDC spare on Standard RAS due to
 adddc_region0_control.nonfailed_cs being overwritten
18.[Hsd-ES]:[2103624281]There is no PTU driver loaded when only plug RDIMM on SUT.
19.[Hsd-ES]:[5387865]klocwork cleanup - platform (remaining items) Klocwork clean up
20.[Hsd-ES]:[5387934]CCB 136520 - Additional changes published in official DSM spec
21.[Hsd-ES]:[5387829]PurleySktPkg/PchIinitPreMem [CLX-AP PO] 2S Fused setup enters Reset loop during 'AC_Reboot'
22.[Hsd-ES]:[1408148493]Latch System Shutdown - LSS Latch option not available in BIOS for WFP
23.[Hsd-ES]:[5387922][Security]RBT read enable (KTIAGCTRL.rbt_rd_enable) not locked - risk if D2C must be disabled for any reason
24.[Hsd-ES]:[5387668]CLONE from skylake_server: in a fully populated system, Alert from multiple AEP can break SMM time latency
25.[Hsd-ES]:[5387928]FVMRC FV Image size exceeds set FV image size 0x200000
26.[Hsd-ES]:[5387935]Cannot create or delete namespace when set_platform_config_date command policy set to 1
27.[Hsd-ES]:[FIV9094]Integrate SPS E5_04.01.03.236.0 to Trunk
28.[Hsd-ES]:[FIV_9409]Integrate IntelDCPersistentMemoryDriver_v01.00.00.3371 to Trunk
29.[Hsd-ES]:[5387865]klocwork cleanup - platform (remaining items) Klocwork clean up
30.[Hsd-ES]:[5387933][Purley-R][2S][IFWI 2018.46.2]The SUT can't boot on AEP with BIOS:560_D08
31.[Hsd-ES]:[5387930]BSSA stitching RMT failed because of mismatching header file
32.[Hsd-ES]:[5387913]DDR-T alerts SCI notifications are required to meet Chet's table
33.[Hsd-ES]:[5387888]CLONE from skylake_server: [google] Intermittently
    non-functional DIMMs in PVT - surprise clockstop
34.[Hsd-ES]:[5387915]"en_pgta2" programming needs to be fixed for when 3DS LRDIMMs popualted with AEP
35.[Hsd-ES]:[5387911]SKX: Remove MRC per bit deskew fix from BIOS
36.[Hsd-ES]:[1506935983]CpPcRestrictedPkg/DualVideo: Add Video Controller Check
37.[Hsd-ES]:[5387865]klocwork cleanup - platform (remaining items) Klocwork clean up of xmlcli and AMI items Part 2
38.[Hsd-ES]:[5387886]CLONE from skylake_server: DDRT Training hung at "CMD Vref
    Centering -- Started" in post code B7 with WW34 BIOS
39.[Hsd-ES]:[5387607]CLX: PBF Support in BIOS Reference Code
40.[Hsd-ES]:[5387825]PurleyPlatPkg/Pci: Incorrect out of I/O resources issues
41.[Hsd-ES]:[2103624158]OS CERT - Win2019- Check SMBIOS Table Specific Requirements test failed.
42.[Hsd-ES]:[1506880179]BiscaynePark PCSD platform BIOS enabling - Initial Code Checkin
43.[Hsd-ES]:[5387850]S3 suspend fails after 30+ iterations with ME11 FW and no Crystal Ridge
    When MSR(0x3A) lock bit is set, Bios still save the rest of MSR(0x3A) into S3 boot script.
44.[Hsd-ES]:[5387901]CrExitBootServices not called during Legacy Boot (CSM), only UEFI Boot
45.[Hsd-ES]:[5387905]Fix restricted tagging for CLX64L/CLXAP that causes external code to deviate from validated code
46.[Hsd-ES]:[Hsd-ES]:[5387825]PurleyPlatPkg/Pci: Incorrect out of I/O resources issues
RP release Reference code version: CP_PURLEY_0560_D10.
This release is mapping to RP daily build:CP_PURLEY_0561_D05.

=============================================================================

                                                     0D.01.0226
================================================================================
1.[Hsd-ES]:[no_sighting]Purley Refresh BIOSID Update to 560
2.[Hsd-ES]:[OSS_0009358]Integrate Microcode 04000010 for CLX B0 from PC-Purley Skylake
3.[Hsd-ES]:[5387865]klocwork cleanup - platform (remaining items) Klocwork clean up of remaining items minus xmlcli and AMI issues
4.[Hsd-ES]:[FIV9327]Update ME AMT FW version to v11.22.60.1561
RP release Reference code version: CP_PURLEY_0559_D18.
This release is mapping to RP daily build:CP_PURLEY_0560_D01.

=============================================================================

                                                      0D.01.0222
================================================================================
1.[Hsd-ES]:[5387898]AEP BIOS must support low and high priority Thermal Error Logs for launch
2.[Hsd-ES]:[5387902]CLONE from skylake_server: [Dell] ESXi GUI doesn't see AEPs under Persistent Memory when "DfxSkuBasedNfitCreation" is Enabled.
3.[Hsd-ES]:[1606695157]Analyze and Fix KW Issues in Purley PCSD project.
4.[Hsd-ES]:[2103623050]MBIST BIOS will halt during POST after trigger MBIST successfully in Mirror mode.
5.[Hsd-ES]:[5387885]the bridge device's endpoint device will not be enabled, if bridge device's
    Secondary & Subordinate Bus Number have the same bus number,
6.[Hsd-ES]:[5387900]Follow up to s5387763 - fixed problem with large payload data in OS mbox for long op in SMM mbox
7.[Hsd-ES]:[5387829]PurleySktPkg/PchIinitPreMem [CLX-AP PO] 2S Fused setup enters Reset loop during 'AC_Reboot'
8.[Hsd-ES]:[FIV9315][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3364 from RP
9.[Hsd-ES]:[5387694]MRC warning code for unsupported AEP needs to distinguish when CPU does not support DDRT
10.[Hsd-ES]:[5387437]ASSERT due to incorrect SAD Interleave List
11.[Hsd-ES]:[5387763]Polling for prior Long Operation Status
12.[Hsd-ES]:[5387827]CLONE from skylake_server: [VMWare] Inconsistent values of "Estimated time for scrub to complete " reported by the start ARS command in WP with ww34 BKC
13.[Hsd-ES]:[1506769247]Fixed WalkerPass Onboard NIC setup page is empty.
14.[Hsd-ES]:[1506860627]Memory Channel/Slot/DIMM Nomenclature for Walker Pass.
15.[Hsd-ES]:[5387830]Cloned From SKX Si Bug Eco: CLONE SKX Sighting: [2LM]  Supercollider + DDR4 ECC hitting kdb with m2mem timeout
16.[Hsd-ES]:[5387825]PurleyPlatPkg/PciHostBridge: Incorrect out of I/O resources issues part2
17.[Hsd-ES]:[NO SIGHTING]Added TwoDieAsOne knob control for CLX-AP system
18.[Hsd-ES]:[5387877]EWL Warnings are not generated for DCPMM invalid configuration for few cases
19.[Hsd-ES]:[5387621]CCB 136530 Need the ability to clear/reset DIMMs to a factory clean state
20.[Hsd-ES]:[5387847]Windows will report WHEA ID 47 event whose Error Source is
 Corrected Machine Check after inject uce non-fatal error on Win2016 via wheahct.exe.
21.[Hsd-ES]:[5387880]Dirty shutdown always being reported in AD mode
22.[Hsd-ES]:[5387429]SMM Mode does not clear AER STS Bits when _OSC Method says Handle Firmware First.
23.[Hsd-ES]:[5387048]2LM error flow, Read-miss UC clean, M2M MCI_address log incorrect
24.[Hsd-ES]:[5387078]1TB CR DIMM Support Backport to CLX
25.[Hsd-ES]:[5387842]ADR Timeout incorrect bios value for 2 sockets
26.[Hsd-ES]:[5385940]HII Export Database Variable is NOT protected This variable is RT so that OS runtime tools can access it. But it is not locked as read only variable. 
27.[Hsd-ES]:[5387748]MRC warning for AEP capacity mismatch on a socket not getting generated in 1LM
28.[Hsd-ES]:[5387682]2LM IMC memory mismatch warning being logged unnecessarily in 1LM
29.[Hsd-ES]:[5387519][CLX-AP] 2 die in 1 support (fix)
30.[Hsd-ES]:[5387552]DMI VC0 and VC1 mapping fixes
31.[Hsd-ES]:[5387882]Override user provided vdd settings when AEP is present on socket
32.[Hsd-ES]:[5387867]CLX-AP: 3-Strike Hang in 4s Ring Config
33.[Hsd-ES]:[5387852]CLONE from skylake_server: Customer Sees MTRR Init issue during DXE SMM Phase
34.[Hsd-ES]:[5387715][IPS 2205540752] Slots coming from CPU 4 RP 2A is getting disabled.
35.[Hsd-ES]:[no_sighting]Integrate MeBx v11.0.0.0011 into TPP BIOS image
36.[Hsd-ES]:[5387812]Iteration only on first socket.
37.[Hsd-ES]:[no_sighting]Integrate SPS E5_04.01.02.224.0 into TPP BIOS image
38.[Hsd-ES]:[FIV9129]Integrate Microcode 01000147 for SKX B1 on TPP
39.[Hsd-ES]:[5387587]TPP SUT with SKX B1 can't bootup and hang b1
40.[Hsd-ES]:[5387777]ACPI DMAR flag set for X2APIC_OPT_OUT
41.[Hsd-ES]:[FIV9244]Update FPK NVM for Lightning Ridge v4.00_80001558 image to trunk
42.[Hsd-ES]:[5385938]ME FW measurement is extended to TPM after 3rd party code execution.
43.[Hsd-ES]:[5387712]RDT "LogUncCorrectedMemError" Messages on Serial Port Log
44.[Hsd-ES]:[5387834]Whea error log ID 17 can't create after inject Correctable PCIe Error
45.[Hsd-ES]:[5387742]2lm, read-hit-clean-correctable , BIOS generates incorrect WHEA log
46.[Hsd-ES]:[5387843]Code Bugs found on implementation of 5386950.
47.[Hsd-ES]:[5387836]KTI uniphy recipe update for CLX-AP
48.[Hsd-ES]:[5387848]MP4 3DS RDIMM 1DPC logging TOR TO running rankSpare
49.[Hsd-ES]:[2206188558]RP BIOS FastGO knob to be available in WFP BIOS
50.[Hsd-ES]:[5387691]CLX systems with large memory size runs out of PEI memory during S3 resume
51.[Hsd-ES]:[5386567]PSIRT-BIOS-2017-025 Untested Memory Not Covered by SMM Protection
52.[Hsd-ES]:[5387738]Multiple error injection to IIO RP not generating SMI.
53.[Hsd-ES]:[1606748561][Purley-Refresh] RAS Sync from RP to PC code 5387232
54.[Hsd-ES]:[1606764270][Purley-Refresh] RAS Sync from RP to PC code 5387686
55.[Hsd-ES]:[5387609][CR] Introduce ASL debug infrastructure and remove ASL/SWSMI DSM switch
56.[Hsd-ES]:[1606762976]BIOS fix for P2P performance.
57.[Hsd-ES]:[1606763374]EV DFX Features BIOS setup knob should not be displayed in setup for user, but can be modified using ITK.
58.[Hsd-ES]:[1606695157]Analyze and Fix KW Issues in Purley PCSD project.
59.[Hsd-ES]:[FIV9226]Update Fort Park NVM v4.00_80001556 image with new OROM to be included in IFWI for Purley 2S
    
60.[Hsd-ES]:[5387801][CLX AP PO] Support 1SPC as Walker Pass requires 1SPC
61.[Hsd-ES]:[2103623986]The System memory detected is incorrect in the POST Diagnostic Screen Display page with 2-2-2 100% memory mode.
62.[Hsd-ES]:[5387462]PCI Slot Implemented bit mechanism
63.[Hsd-ES]:[5387747]move ADR setup outside DFX menu
64.[Hsd-ES]:[1506864565]Update Ssid_Svid.
65.[Hsd-ES]:[FIV9216]Integrate CLX B1 debug patch mbf50657_8500000f
66.[Hsd-ES]:[2103621956]Windows will report WHEA ID 47 event whose Error Source is Corrected Machine Check after inject uce non-fatal error on Win2016 via wheahct.exe.
67.[Hsd-ES]:[FIV9215]Integrate  CLX B0 debug patch mb750656_8400000f
68.[Hsd-ES]:[5387329]Change default value of DMI NoSnoopOpWrEn
69.[Hsd-ES]:[5387800] CAPID values are only populated on socket0
70.[Hsd-ES]:[5387868]Setup Variable Checker scripts should be flagged as Restricted for the external source
71.[Hsd-ES]:[FIV9205]Integrate IntelDCPersistentMemoryDriver_v01.00.00.3359 to Trunk
72.[Hsd-ES]:[5387849]Ganges knob programming broken in plyxint1.86b.0554.D33
RP release Reference code version: CP_PURLEY_0558_D08.
This release is mapping to RP daily build:CP_PURLEY_0559_D15.

=============================================================================

                                          0D.01.0202
================================================================================
1.[Hsd-ES]:[2204324560,1506729082]Adding setup knobs to PCSD
2.[Hsd-ES]:[2103623845]There are two WHEA ID 22 event after inject MBE on windows.
3.[Hsd-ES]:[5387651]firmware default setting to production readiness This is a formal request to make our CRB BIOS default setting as Production BIOS worthy.
4.[Hsd-ES]:[5387825]Incorrect handling of IO resources for socket
5.[Hsd-ES]:[5386177]CLONE from skylake_server: From server_sw_fw_nvm: IFC value in NFIT is set incorrectly (basing on SAD rules vs from NVDIMM SPD)
6.[Hsd-ES]:[5387799]Manufacturer of AEP DIMM will show UNKNOWN in BIOS Memory Topology Page
7.[Hsd-ES]:[5387835]Need to rename CLX64L board type folder without Restricted.
8.[Hsd-ES]:[5387861]New Operating Mode value for detecting Ignition Firmware by BIOS
9.[Hsd-ES]:[1805886447]PurleySktPkg/PchIinitPreMem [CLX-AP PO] 2S Fused setup enters Reset loop during 'AC_Reboot'
10.[Hsd-ES]:[1606748952]Expose AdrEn setup option if DCPMM present and have AppDir.
11.[Hsd-ES]:[5387519]Revert "5387519: [CLX-AP] 2 die in 1 support"
12.[Hsd-ES]:[5387821]- DIMM rank number and DIMM Type report on SMBIOS table
              are not aligned with DCPMM
13.[Hsd-ES]:[2103623825]The behavior of processor cores disabled via ipmi is incorrect with CLX B0 CPU QQZ7.
14.[Hsd-ES]:[5387846][CR]ARS Ended Prematurely logic needs correction
15.[Hsd-ES]:[1506135329][CLX-R] #CCB2231 Behavior of system with invalid AEP configuration (BIOS EPS needs update as well) - Recheckin
16.[Hsd-ES]:[2103623383]NVMeSSD led is amber blinking during boot process when install NVMe SSD into HSBP through by 4 port Retimer card
17.[Hsd-ES]:[1506860670]CLX SPS FW NMPTU  limitation:Only allow NMPTU dispatch when without AEPDIMM or AEPDIMM in memory 2LM mode
18.[Hsd-ES]:[5387773]2LM capacity not surfaced if provisioned first in 1LM then switched to 2LM
19.[Hsd-ES]:[1506755655][OOB BIOS Configuration]EWS show some variables when SUT without install related device. mismatch bios setup that can't find related variables.
20.[Hsd-ES]:[5387735][SKX] ]DCPMM SPD "SPDMMfgId" not defined for AEP Memory
21.[Hsd-ES]:[5387844][CR] Low priority error handling is broken
22.[Hsd-ES]:[5387725][CR] Incorrect NVDIMM Region Mapping SPA offset in NFIT Table
23.[Hsd-ES]:[5387818]Dirty ShutDown Error Injection using _DSM function Index 18 returns status "6, unknown error"
24.[Hsd-ES]:[5387519][CLX-AP] 2 die in 1 support
25.[Hsd-ES]:[no_sighting]Integrate SKX H0 patch mb750654_02000055 to trunk
;Integrate CLX B0 patch mbf50656_8400000e to CLX AP
;Integrate CLX B0 patch mbf50656_8400000e to trunk ACMDBG
;Integrate CLX B1 patch mbf50657_8500000e to trunk ACMDBG
26.[Hsd-ES]:[OSS_0008894]Integrate Microcode 02000056 for SKX H0 from PC-Purley Skylake
27.[Hsd-ES]:[5387803]CLX A0 CPU core/thread number is wrong under windows OS device manager
28.[Hsd-ES]:[2103623598][STP-R] Windows 2016 OS cert signed Driver check(CheckLogo) fail that OS had unknown device with BIOS D01.0125
29.[Hsd-ES]:[5387626]Twice write to PCH SLP_TYP/SLP_EN registers in power button SMI event
30.[Hsd-ES]:[2103623093]The NIC1 Port1/Port2 can not disable in the Legacy mode 
31.[Hsd-ES]:[1606738103][SDP]:BIOS knobs exposed for WW41 BKC sync with SDP
32.[Hsd-ES]:[FIV9109][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3354 from RP
RP release Reference code version: CP_PURLEY_0557_D09.
This release is mapping to RP daily build:CP_PURLEY_0558_D04.

=============================================================================

                                              0D.01.0192
================================================================================
1.[Hsd-ES]:[1506135329] [CLX-R] #CCB2231 Behavior of system with invalid AEP configuration (BIOS EPS needs update as well) - Workaround
2.[Hsd-ES]:[5387093]Fixed compilation and scripts after ipclean
3.[Hsd-ES]:[5387811]PurleySktPkg/PeiPchInitLib [LBG HSIO] HSIO_TX_DWORD6 for SATA/sSATA didn't been programmed as expected.
4.[Hsd-ES]:[2103623816]Boot manager still can see related boot entry while disable IPv4/IPv6 PXE support option
5.[Hsd-ES]:[5386076][MRC][CLX] [2933] DDR4 Training--DRAM RxEq training and Modified RX CTLE
 Training
6.[Hsd-ES]:[5386564]Fixed the timestamp zeroing error that allowed certificate rollbacks
7.[Hsd-ES]:[5387828][CLX AP PO] CLX-AP PLatform doesn't boot with Ch4 slot 1 populated
8.[Hsd-ES]:[5387720] Accessing Bootscript save after SmmReadyLock is set
9.[Hsd-ES]:[5387576]It's not reasonable to make PPR feature functional with PPR error injection enable
10.[Hsd-ES]:[5387638] CLX_B0_Pcode_patch MirrFailOvr Injection DXE assert on QQNT
11.[Hsd-ES]:[5387771] Implement Setup Option and Code to Disable L2 RFO Prefetching
 MSR 0x972[3].
12.[Hsd-ES]:[no_sighting] Purley Refresh BIOSID Update to 557
13.[Hsd-ES]:[2202066319] Adding SDP Build option
14.[Hsd-ES]:[5387822] CLONE from skylake_server: DDRT_HWM_THRSH and DDRT_HWN_DRAIN_THRSH not set correctly with WW42 BKC
15.[Hsd-ES]:[1506135329] [CLX-R] #CCB2231 Behavior of system with invalid AEP configuration (BIOS EPS needs update as well)
16.[Hsd-ES]:[221795:[SDL] [Opal Smm] BlockSid setting may be disabled after return from S3
17.[Hsd-ES]:[1606713373] [Purley-Refresh] RAS Sync from RP to PC code 5387434
18.[Hsd-ES]:[5387749] 2LM IMC memory mismatch warning being logged in DDR only configuration
19.[Hsd-ES]:[2103623756] There is no "Storage Controller"options show up in UEFI Option ROM Control page when enable RSTe RAID mode.
20.[Hsd-ES]:[5387769] BIOS does not change BoardID with Simics VP model
21.[Hsd-ES]:[2202478376] Correct the content of mDimmToBankLocator and mDimmToDevLocator arrays
22.[Hsd-ES]:[5387766] [IPS 2202878155] Getting corrupted messages with debug tools coming from DXE Driver
23.[Hsd-ES]:[5387488] [SDL] CCG report OPAL password issue
24.[Hsd-ES]:[5387790] CLX AP PCIe update
25.[Hsd-ES]:[2007496960] [AT_CLX]  Drives were alarmed when VMD is disabled in BIOS
26.[Hsd-ES]:[2103623558] 0x8461 SEL log not generate when remove power cord to terminate backup bios update
27.[Hsd-ES]:[FIV9058] Integrate IntelDCPersistentMemoryDriver_v01.00.00.3346 to Trunk
28.[Hsd-ES]:[no_sighting] Purley Refresh BIOSID Update to 555
29.[Hsd-ES]:[OSS_0009041] Integrate SPS E5_04_01_02_224_0 to Trunk
30.[Hsd-ES]:[5387503] FW-UEFI-Vuln-2018-014 Stack Overflow on Corrupted BMP
31.[Hsd-ES]:[5387612] CCB 136520 Set Master Passphrase DSM function added
32.[Hsd-ES]:[5387633] fixed linking error
RP release Reference code version: CP_PURLEY_0555_D03.
This release is mapping to RP daily build:CP_PURLEY_0557_D05.

=============================================================================
                               0D.01.0180
================================================================================
1.[Hsd-ES]:[FIV9044][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3344 from RP
2.[Hsd-ES]:[no sighting]Clean unused socket mask variable.
2.[Hsd-ES]:[1407408624,2205563452,1606731772,1606731773,2205463077,2205549243,1806454591]To expose few setup knobs in PC pkg.
3.[Hsd-ES]:[5387808] Skip reporting failing dev on AEP DIMM.
4.[Hsd-ES]:[FIV9041]Integrate SPS E5_04.01.02.224.0 to Trunk
5.[Hsd-ES]:[5387709] Adding more debug output.
6.[Hsd-ES]:[FIV9044]Integrate IntelDCPersistentMemoryDriver_v01.00.00.3344 to Trunk
7.[Hsd-ES]:[5387805]SUT with AEP hang on 0F and can not boot
8.[Hsd-ES]:[5387734]CLONE from skylake_server: From server_sw_fw_nvm: Infinite Short ARS loop after injecting errors and rebooting the platform.
9.[Hsd-ES]:[5387776][CLX-AP PO] CCC Delay Table needs to be updated to include Internal Si Delay
10.[Hsd-ES]:[5387633]copy spi image to workspace
11.[Hsd-ES]:[5387686][Dell] [RAS] SpaToNvmDpa() routine does not work
12.[Hsd-ES]:[5387659]KTI uniphy recipe updated for CLX-AP values
13.[Hsd-ES]:[5387711]Add conditional compile switch to all #defines and code pertaining only to CLX64.
14.[Hsd-ES]:[5387491]Incorrect Error Location for Memory Correctable Error in case of 2nd Error
15.[Hsd-ES]:[5387785]Update CLX-AP ucode patch to 83100a0e
16.[Hsd-ES]:[5387742]2lm, read-hit-clean-correctable , BIOS generates incorrect WHEA log
17.[Hsd-ES]:[5387765]LSS Reason code for CLEAN_LSS_S3_POWER_FLOW invalid
18.[Hsd-ES]:[5387798][Purley-R][CR-2S]After format AEP with bios 554D10, then can't modify the AEP mode
19.[Hsd-ES]:[5387781]Namespace goes missing after BKC41.5 update
 
20.[Hsd-ES]:[2205548053]RP BIOS knobs for IODC options not found in WFP BIOS
21.[Hsd-ES]:[1506780000][Purley] There is a coding style issue with CL528438
22.[Hsd-ES]:[1506769352]Walker Pass onboard video controller is disabled even there is no AIC video card installed
23.[Hsd-ES]:[1504687190]No memory error event logged into SEL and Event Viewer after Uncorrectable Error injected in independent mode.
24.[Hsd-ES]:[OSS_0008739]Update ESRTIISataEfi 05140000
25.[Hsd-ES]:[FIV8968][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3342 from RP
26.[Hsd-ES]:[5387760]Change CLX64L board type detection structure
27.[Hsd-ES]:[5387165]Incorrect failed device value reported in eMCA elog when corrected error is injected in 1LM DDR4
28.[Hsd-ES]:[5387787]RankSparing TOR TO mailbox not ready
29.[Hsd-ES]:[5387605]CLONE from skylake_server: Request to Split DDRT alert bit 0 to have Media and Thermal Separated
30.[Hsd-ES]:[5387726]CLX: changes to IIO-RC needed to enable CLX-64L - part1 - resubmit
31.[Hsd-ES]:[5387784]Address Translation Broken With WW36 Drop [IPS 2205561435]
32.[Hsd-ES]:[5387625]CCB 136558 Host Accessible AEP Performance Knobs [Updated]CCB 136558 Host Accessible AEP Performance Knobs [Updated]
33.[Hsd-ES]:[5387564]Mem timing request to remove the specMin from the Memdebugprint when using RDIMM
34.[Hsd-ES]:[OSS_0008874]Integrate Microcode 0300000f for CLX A0 from PC-Purley Skylake
    
35.[Hsd-ES]:[OSS_0008875]Integrate Microcode 02000055 for SKX H0 from PC-Purley Skylake
36.[Hsd-ES]:[5387338]Optimize MTRR initialization in Intel ref code including S3 resume
37.[Hsd-ES]:[BIOSACM OSS_0008852/SINIT OSS_0008854]Update Production BIOSACM 1.6.6/SINIT 1.6.6
38.[Hsd-ES]:[OSS_0008877]Integrate SPS E5_04_01_02_223_0 to Trunk
39.[Hsd-ES]:[FIV8873]Update ME AMT FW version to v11.22.0.1543
40.[Hsd-ES]:[2103623341] HTTP boot with img file can not boot properly.
41.[Hsd-ES]:[FIV8875]Integrate SKX H0 patch mb750654_02000055 to trunk
42.[Hsd-ES]:[FIV_0008778] Update RSTeSataEfi version to 6.0.0.1014 for CLX AP ini
43.[Hsd-ES]:[FIV8852/FIV8854]Integrate BIOSACM/SINIT 1.6.6 NPW
44.[Hsd-ES]:[1506778874]Fix Walker Pass onboard TPM device is not detected.
45.[Hsd-ES]:[FIV8881][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3332 from RP
46.[Hsd-ES]:[5387189] Not able to boot when MEMTRIP option is set to enabled in bios
47.[Hsd-ES]:[FIV8874]Integrate CLX A0 patch mb750655_0300000f to Trunk
48.[Hsd-ES]:[5387726] CLX: changes to IIO-RC needed to enable CLX-64L-part1
49.[Hsd-ES]:[5387675]Code Bugs in Intel Reference Codes
50.[Hsd-ES]:[5387545]- CCB 136540 FIS 1.13 Release
51.[Hsd-ES]:[5387709] Integrating BIOS setup variable checker script into build system.
52.[Hsd-ES]:[5387757] CLONE from skylake_server: [google] WW28 data center deployment failures - context block failures
53.[Hsd-ES]:[5387774] [CR] Unable to Start ARS when socket count > 1
54.[Hsd-ES]:[1506657447]PC RAS -  NMI was triggered for Memory uncorrectable error
RP release Reference code version: CP_PURLEY_0554_D33.
This release is mapping to RP daily build:CP_PURLEY_0554_D35.

================================================================================
                               0D.01.0159
================================================================================
1.[HSD-ES]:[5387726] CLX: changes to IIO-RC needed to enable CLX-64L-part1
2.[HSD-ES]:[5387502] FW-UEFI-Vuln-2018-011 Buffer Overflow in BlockIo service for RAM disk
3.[HSD-ES]:[5387236] Enable A17 for row address in CpgcPprTestGlobalSetup
4.[HSD-ES]:[5387664] For 16Gb based DIMMs, BIOS needs to force tRFC1=550ns, tRFC2=350ns, tRFC4=260ns
5.[HSD-ES]:[5387770] Socket Memory Variable out of sync with Skylake Production trunk
6.[HSD-ES]:[5387093] GCC:Various fixes for Bash scripts after IP Clean
7.[HSD-ES]:[1606695877] [Purley-Refresh] RAS Sync from RP to PC code 5387354,5387522,5387423
8.[HSD-ES]:[5387686] SpaToNvmDpa() routine does not work
9.[HSD-ES]:[5386893]  Improper Decoding of Enhanced Warning Log type 8 and type 9 [IPS 2202688299/226392]
10.[HSD-ES]:[1506636954] WFP: Sync RAS changes from RP to PC (“NVMCTLR High Priority Error Signaling” setup option)
11.[HSD-ES]:[2202066319] SDP: Submit SDP code/menu changes to repo as build option
12.[HSD-ES]:[5387048] 2LM error flow, Read-miss UC clean, M2M MCI_address log incorrect
13.[HSD-ES]:[5387653] SKX: Import MRC per bit deskew fix from 10nm
14.[HSD-ES]:[5387717] DSM- reset the ADWB Flush Loop Status to FAILURE
15.[HSD-ES]:[5387599] CCB 136460: Remove the stop booting (hang) requirement from CCB 135735 and allow one DIMM to train
16.[HSD-ES]:[5387211] MRC:BSSA API and RMT changes for CLX RPQ hang fix
17.[HSD-ES]:[5387497] CLONE from Tiano:[SDL] PSIRT-BIOS-2017-025:SMM need mark untested memory to be not-present for SMM communication buffer
18.[HSD-ES]:[5387093] Various fixes for Bash scripts after IP Clean
19.[HSD-ES]:[5387610] Add Error Message if Bios Boot is Halted by Corrupt AEP Media Log
20.[HSD-ES]:[5387739] CLONE from skylake_server: iMC dimmmtr_1 register dimm_pop bit set incorrectly for Media Disabled AEP DIMMs
21.[HSD-ES]:[5387700] Inconsistent AEP capacity for 2LM and AppDirect mode
22.[HSD-ES]:[5387613] [Purley-R-CLX] BIOS does not skip Intel ME related tasks when ME is not functional
23.[HSD-ES]:[5387707] [CI] Request to add new build flag to disable AMT code with WS Slim SKU and ME support
24.[HSD-ES]:[5387558] CLONE from skylake_server: The platform configuration check hasn't detected that interleave set is broken because the DIMM(s) were moved
25.[HSD-ES]:[5387659] KTI uniphy recipe updated for CLX-AP values
26.[HSD-ES]:[5387155] CLX-AP [RAS]:  Fix MAXCOREBITS in RAS code to support extended no. of cores in CLX-AP
27.[HSD-ES]:[5387382] - [AD WB]Implement error status check and update
28.[HSD-ES]:[5387598] CCB 136546 Add Warnings if DCPMMs on CPU socket are not partitioned identically
29.[HSD-ES]:[5387232] Altera FPGA PCIe Error Handler feature request to check PCIe device's mask
30.[HSD-ES]:[5387501] CLONE from Tiano: [SDL] PSIRT-BIOS-2017-030 FV Alignment in EDK2 Chain-of-Trust Bypass
31.[HSD-ES]:[5387669] CLONE from skylake_server: [CR BKC][2018_WW37][P&P] Windows RS5 SPECpower score decreased from 8960 to 8150,regression 9%
32.[HSD-ES]:[5387593] Need to report status codes in Intel RC drivers.
33.[HSD-ES]:[5387616] Add fast boot mode support on Purley BIOS for boot performance enhancement
34.[HSD-ES]:[FIV8806] Integrate IntelDCPersistentMemoryDriver_v01.00.00.3316 to Trunk
35.[HSD-ES]:[5387657] [SSDT OEM1 Table] CPU Ratio Report Wrong Value While Maximum Ration been Set the Same as Minimum Ratio
36.[HSD-ES]:[5387733] Additional debug code needed in AddCpuSmbiosTables function in CpuSmbios.c
37.[HSD-ES]:[5386851] AcpiPlatformHooks.c assert when NVDIMM is used
38.[HSD-ES]:[5387701] Do not report errors on valid but non PMEM address used in CR RAS
39.[HSD-ES]:[5387093] GCC build is broken in TC
40.[HSD-ES]:[5387181] CLONE from skylake_server: From server_sw_fw_nvm: When injecting/clearing poison errors outside PMEM range BIOS does not error out
41.[HSD-ES]:[1506744997] [OOB BIOS Configuration]Some variables can find in BIOS setup but can't find in EWS
42.[HSD-ES]:[FIV8778] PurleyPcPkg\StitchingPkg:[PC Stitching]Update RSTeSataEfi version to 6.0.0.1014 for RP
43.[HSD-ES]:[1506767920] Sync WalkPass PPO Change to AcadiaPark
44.[HSD-ES]:[1506765606] Sync RP dimm isolation change to PC RAS code
45.[HSD-ES]:[0005386566] Fixed tiano compress out of spec behavior that caused security vunerability
RP release Reference code version: CP_PURLEY_0554_D10.
This release is mapping to RP daily build:CP_PURLEY_0554_D14.

===============================================================================
                               0D.01.0147
================================================================================
1.[HSD-ES]:[5387611] Current BIOS is not disabling A17 for 16Gb based x8  DIMMs, causing CMD CLK failures
2.[HSD-ES]:[5387606] CLX: Update Intel Speed Select Core Selection Algorithm to support Off Axis SKUs[HSD-ES]:[5387685] Platform unable to boot when bios knob "ProcessorAutonomousCstateEnable" is enabled
3.[HSD-ES]:[5387702] DXE assert in crystalridge driver after enabling the 1LM mirroring on a platform in 2LM mode
4.[HSD-ES]:[5387728] - SUT can not enter S5 and will auto reboot with memorymode
 Auto/2LM in BIOS
5.[HSD-ES]:[5387496] CLONE from Tiano: [SDL] PSIRT-BIOS-2017-019: Timestamp zeroing issue on APPEND_WRITE
6.[HSD-ES]:[1506755045]Update softstrap setting for Acadia Park
7.[HSD-ES]:[5387189] Not able to boot when MEMTRIP option is set to enabled in bios
8.[HSD-ES]:[5387515] PECI Crashdump code not setup correctly
9.[HSD-ES]:[5387661] klocwork cleanup - override modules
10.[HSD-ES]:[5387683] PWRBTN on Dragon Rock inoperative.
11.[HSD-ES]:[5387722] [CLX B1 PO] : BIOS detection for CLX B1
12.[HSD-ES]:[5387591] Remove garbage character from uni files
13.[HSD-ES]:[1506111824] merge A0 PPO changes into trunk
14.[HSD-ES]:[FIV8718] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3300 from RP
15.[HSD-ES]:[5387463] CLONE from skylake_server: [CR BKC][2018_WW29]Last Shutdown Status CANNOT get value 0x94 after S5 cycle
16.[HSD-ES]:[5387544] Add M2MTO reason codes to Boot Status Register of AEP in support of link failure workaround
17.[HSD-ES]:[5387156] Add support to report FRU information in Error Logs based onCLX-AP 2 dice in 1 Skt
18.[HSD-ES]:[5387420] SMBIOS tables related to memory should show Effective memory size for Example Type 19
19.[HSD-ES]:[1506760869] Update IIO bifurcation setting for Acadia Park
20.[HSD-ES]:[5385934] [HaT] UEFI variable corruption will DoS system
21.[HSD-ES]:[1506754951] Update PCH GPIO Settings on Acadia Park
22.[HSD-ES]:[5387631] [RDT] [CLX] [CMT-CAT] New recommended perf settings for Cache Ways
23.[HSD-ES]:[5387557] CLONE SKX Sighting: System CATERR when Hynix 8GB 1RX8 with Inphi register mix 32GB 2RX4 DIMMs
24.[HSD-ES]:[5386604] ACPI table will miss some core after disable core
25.[HSD-ES]:[5387489] Platform Stuck in Bios Boot Infinite Loop - LogUncCorrectedMemError
26.[HSD-ES]:[5387490] Microsoft Azure requires BIOS helper routine to provide interpreted LSS and LSS reason
    
27.[HSD-ES]:[5387572] Provide Platform Interpreted Unlatched Dirty Shutdown Count Clean/Dirty indicator & reason for clean/dirty
28.[HSD-ES]:[5387239] [CR MTO] The current RAS code for PCIe errors scans the topology below the offending root port for all PCI-e devices which hogs the CPU time in SMM code.
29.[HSD-ES]:[5387538] klocwork cleanup - crystal ridge
30.[HSD-ES]:[1506757895] [OOB Firmware Update] The sensor name format about BIOS image update  SEL  is unexpected.
31.[HSD-ES]:[2103623411] There is no SEL log generate when flash BIOS and ME version which same as SUT version.
32.[HSD-ES]:[5387690] Update CLX-AP ucode/pcode to mbf50655_8310090e
33.[HSD-ES]:[5387423] [MTO] PCH error logging not working
34.[HSD-ES]:[5387526] CLONE from skylake_server: [Dell]Locked/Illegal Access when booting to OS
35.[HSD-ES]:[5387440] OverrideDefaultBifSlots_SKX' and OverrideDefaultBifSlots violate UBA
36.[HSD-ES]:[5387425] UEFI SMM Driver used gBS->LocateProtocol() rather than used gSmst->SmmLocateProtocol().
37.[HSD-ES]:[5387559] CCB 136525 Request ability to allow access to the Namespace Label area while blocking access to the other two
38.[HSD-ES]:[2103622971] [Promote.rej---commercial BIOS] The memory size shows at POST is wrong.
39.[HSD-ES]:[2103623264] VMD enable in BIOS is mismatch with motherboard NVME SSD.
40.[HSD-ES]:[5387524]MLC_WD_Timer 3-strike errors when installed memory = MMIO High base
41.[HSD-ES]:[2103621961] Total DDR4 memory in mirror mode is twice than total physical DDR4 memory on 1LM+AD mode config.
42.[HSD-ES]:[5387678] KTI code needs to accommodate stack4 on CLX-AP
43.[HSD-ES]:[5387665] [Purley][2S][IFWI2017.50.3.03.0218]we cannot find ExecutePPR - Post-PPR Row test - passed in serial log while injecting error to memory and then reset SUT with Hard PPR enabled.
44.[HSD-ES]:[5387628] CLX A0 - High CPU Utilization during 2LM boot.
45.[HSD-ES]:[5387684] CPU stepping check throws warning on CLX-AP A0
RP release Reference code version: CP_PURLEY_0553_D13.
This release is mapping to RP daily build:CP_PURLEY_0554_D02.

===============================================================================
                               0D.01.0134
================================================================================
1.[HSD-ES]:[OSS_0008679] PurleyPCPkg/StitchingPkg/Microcode:CLX B0 ucode
2.[HSD-ES]:[5387559] Revert CCB 136525 Request ability to allow access to the
 Namespace Label area while blocking access to the other two
3.[HSD-ES]:[FIV8669] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3286 from RP
4.[HSD-ES]:[1506755045] Update softstrap setting and remove unused files for Acadia Park
5.[HSD-ES]:[5387683] PWRBTN on Dragon Rock inoperative.
    
6.[HSD-ES]:[2205036598]iafw-purley/Purley Refresh: Purley Refresh BIOSID Update to 553
7.[HSD-ES]:[5387586] DDR-T POR compatibility checks should be conditioned on EnforcePOR setting
8.[HSD-ES]:[2103622380] [STP-R]SMBIOS type20 table has failures found if DIMM populated in each imc
9.[HSD-ES]:[1407868346] Need ARS on Boot BIOS option for WolfPass Platform
10.[HSD-ES]:[OSS_0008790]  Integrate SPS E5_04_01_02_209_0 to Trunk
11.[HSD-ES]:[5387216] PurleySktPkg\ProcMemInit Four Socket Skylake systems in an endless reboot in MRC after a warm boot
12.[HSD-ES]:[5387654] PurleyRpPkg/Uba: DRK PPO changes
13.[HSD-ES]:[5387590] MRC: Power TrendLine Calculation serial log output issues
14.[HSD-ES]:[5387517] mHost.setup.cpu.EnableGv is always set to 0 even EIST setup is set.
15.[HSD-ES]:[5386996] Print Apache Pass DIMM location consistently in CrystalRidge DXE driver
16.[HSD-ES]:[5386177] CLONE from skylake_server: From server_sw_fw_nvm: IFC value in NFIT is set incorrectly (basing on SAD rules vs from NVDIMM SPD)
17.[HSD-ES]:[5387604] Allow access to DIMM from OS in case of Media Disabled scenario
18.[HSD-ES]:[5387561] Add needed PEI and DXE drivers for a separate CLX64L platform BoardID requirement
19.[HSD-ES]:[5387093] PurleyPlatPkg, PurleyRpPkg, PurleySktPkg: GCC build is broken in TC
20.[HSD-ES]:[5387418] - SMM Flush Handler code refactoring to ease with
 eADR support integration
21.[HSD-ES]:[5387376] SocketMemoryVariable.h in iafw-purley repo is out of sync with the structure used in PLR7
22.[HSD-ES]:[5387640] When DDR4 is added or removed some of the namespaces on AEP disappear
RP release Reference code version: CP_PURLEY_0553_D01.
This release is mapping to RP daily build:CP_PURLEY_0553_D02.

===============================================================================
                               0D.01.0125
================================================================================
1.[HSD-ES]:[FIV8815] Integrate IntelDCPersistentMemoryDriver_v01.00.00.3279 to Trunk

2.[HSD-ES]:[5387563] Fix offset calculation for MC0_DP_CHKN reg 
3.[HSD-ES]:[5387594] 16Gbit 1DPC Ch0 RankSpare causing TOR TO
4.[HSD-ES]:[5387608] Need to undo perf impacting starve threshold setting via a knob
5.[HSD-ES]:[5387637] CLONE from skylake_server: From server_sw_fw_nvm: Enabling Viral Status in BIOS has no effect on ViralPolicy in UEFI CLI
6.[HSD-ES]:[5387530] [CR] Smbios.txt Table has missing Cache DRAM value
7.[HSD-ES]:[HSD-ES]:[FIV8796] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3277 from RP  
8.[HSD-ES]:[5387381] Implement code to wait for IIO Flush completion before WBINVD
9.[HSD-ES]:[5387422] struct BIOS_ACPI_PARAM is incompatible for 8 sockets
10.[HSD-ES]:[5387579] CLONE from skylake_server: C/A parity disabled leads to DDR4 read error
11.[HSD-ES]:[1506737213] AcadiaPark PCSD platform BIOS enabling - Initial Code Checkin
RP release Reference code version: CP_PURLEY_0551_D03.
This release is mapping to RP daily build:CP_PURLEY_0551_D03.
================================================================================
                               0D.01.0118
================================================================================
1.[HSD-ES]:[2103623334] Execute Disable Bit always show "Enable" via bitTest or RU no matter this option set to disable or enable.
2.[HSD-ES]:[5387617][ME] BIOS should wait before calling HeciResetInterface function (HECI SMM driver)
3.[HSD-ES]:[1506741342] Expose "XPT prefetch option for CLX
4.[HSD-ES]:[FIV8583/FIV8582] Integrate BIOSACM/SINIT 1.6.5 NPW into FPGA
5.[HSD-ES]:[5387614] [CR] Remove parameter "BOOLEAN UseOsMailbox" from Crystal Ridge Protocol
6.[HSD-ES]:[FIV8756][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3275 from RP
7.[HSD-ES]:[5386993] DisplaySADTable()  accessing structure incorrectly, could cause buffer overflow.
8.[HSD-ES]:[5387619] PurleyPlatPkg/AddressTranslationDsm: Fix yellow bang
9.[HSD-ES]:[5387585] CLONE from skylake_server: From server_sw_fw_nvm: Bios report that ADR is supported when is disabled
10.[HSD-ES]:[2103623343] There have some BIOS UI show abnormal.
11.[HSD-ES]:[1606379479] To make visible "Force 1-ch way in FM" setup option.
12.[HSD-ES]:[FIV8723][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3273 from RP
13.[HSD-ES]:[5387522] [IPS 2204323964] (PurleyRefresh) System hangs when both DDR4 + AEP DIMM
14.[HSD-ES]:[5387428]_and_5387574: CLONE SKX Sighting: [CLX B0 PO] [1LM] 2DPC 16Gb LRDIMM giving PCU error
15.[HSD-ES]:[5387577] Dq Swizzle Discovery Function might NOT get correct result as exactly physical layout.
16.[HSD-ES]:[1506738461] Enable CLX-AP build target
17.[HSD-ES]:[5387541] DDR-T POR Compatibility check implementation bug with RDIMM configs
18.[HSD-ES]:[5387548] Rename 2LM, AD directory disable knobs
19.[HSD-ES]:[5387543] Remove confusing comment in PchPm.c
20.[HSD-ES]:[5387523] Hang when enabling BSSA RMT and Fast Cold Boot Mode [IPS 220569485]
21.[HSD-ES]:[5387540]Fpdt SMM and S3 resume measurement missing
22.[HSD-ES]:[5387603] Bios knob knob to overriding the current ASL/SMM knob for LSR
23.[HSD-ES]:[5386823] [IPS 2202008173]: AcsCapCount restricted to 100
24.[HSD-ES]:[CCB2334] [Purley PSIRT Factory BMC & BIOS] enabling one-time software update to any version'
25.[HSD-ES]:[FIV8697][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3270 from RP
26.[HSD-ES]:[2103622971] [WFP CLX] BIOS update event display incorrect on SEL.
27.[HSD-ES]:[2103623230] [STP-R] There is unknown device yellow bang in Win2016 device manager
28.[HSD-ES]:[1506438489] [Purley CLX BIOS]Speed Select support in WFP via RSD FW Extensions Spec
RP release Reference code version: CP_PURLEY_0550_D10.
This release is mapping to RP daily build:CP_PURLEY_0550_D13.
================================================================================
                               0D.01.0108
================================================================================
1.[HSD-ES]:[1706845500] [Purley-Refresh] sync RP RAS fix to PC RAS code - 5387224
2.[HSD-ES]:[5387566]: [CR] Bug in PCD update error handling path (porting 10nm 1806407621)
3.[HSD-ES]:[1506459248] [Purley-R] bios_wp module is failed with first boot after online update(backup BIOS updated together)
4.[HSD-ES]:[5387600] Add updated Microcode patch to CLXAP bios code base.
5.[HSD-ES]:[1506731999] there is no warning message in sel log when update corrupt BIOS via OOB FW update
6.[HSD-ES]:[FIV8640] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3262 from RP
7.[HSD-ES]:[5387554] [SKX][CLX][MMRC] Spreadsheet and AutoGenerated code are out of sync
8.[HSD-ES]:[5387335] CrystalRidge.c : Clear cache before and after Error Injection
9.[HSD-ES]:[5387413] AEP: BKC WW24 does not get Label Data for older AEP version
10.[HSD-ES]:[5387581] [CR] Follow up to s5387484 - remve SMBIOS Managemnt Info Structure completely
11.[HSD-ES]:[5387480] [CR] BIOS does not print the contents of the EKV BSR register
12.[HSD-ES]:[150670552 [Purley-R] CLX BIOS security revision is not the same version as Purley sustaining BIOS for easier online upgrade/downgrade testing under normal mode
13.[HSD-ES]:[2103623201]: The name of DCPMM device is "AEP DIMM" on DIMM Information page in Setup UI.
RP release Reference code version: CP_PURLEY_0549_D13.
This release is mapping to RP daily build:CP_PURLEY_0550_D03.
================================================================================
                               0D.01.0093
================================================================================
1.[HSD-ES]:[FIV8584] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3257 from RP
2.[HSD-ES]:[5386793] 3DS L/RDIMM modules reporting core ttmings(tCL-tRCD-tRP)
3.[HSD-ES]:[FIV8574] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3250 from RP
4.[HSD-ES]:[5387480] [CR] BIOS does not print the contents of the EKV BSR (d_fw_status) register
5.[HSD-ES]:[5387464] [RAS] BIOS implementation processes old mailbox entries after getting a DDR-T interrupt
6.[HSD-ES]:[5387321] CLONE from skylake_server: From server_sw_fw_nvm: The platform configuration check hasn't detected that interleave set is broken because the DIMM(s) were moved
7.[HSD-ES]:[5387486] Memory Manufacturer Kingston is misspelled as "Kinston"
8.[HSD-ES]:[FIV8549] [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3246 from RP
9.[HSD-ES]:[5387493] [DDR4 ] CLX BIOS ID 546.D06 Fails on MemTest
10.[HSD-ES]:[5387037] Extra DisableChannel when LateConfig fails getting AEP power management policy [IPS 2203075195]
11.[HSD-ES]:[2007015469] DIMM LED (chX) turns off after another correctable error is injected to a DIMM in different Channel (chY) - V01
RP release Reference code version: CP_PURLEY_0549_D02.
This release is mapping to RP daily build:CP_PURLEY_0549_D03.		

================================================================================
                               0D.01.0083
================================================================================
1.[Hsd-ES]:[5387319][Devious Mind] Very low DDR and DDRT BW observed requiring a reset to clear it.
2.[Hsd-ES]:[OSS_0008495] Integrate Microcode 02000050 for SKX H0 from PC-Purley Skylake
   
3.[Hsd-ES]:[OSS_0008496] Integrate Microcode 01000145 for SKX B1 from PC-Purley Skylake
4.[Hsd-ES]:[FIV8505][PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3242 from RP
5.[Hsd-ES]:[5386230]PCH UEFI FW shall delay PCI Bus Master Enable (PCICMD.BME) until end of POST to prevent DMA attacks on UEFI FW in RAM
6.[Hsd-ES]:[5387350] CCB 136502 AEP 64GB Low-Effort and Fast-to-Market SKU
7.[Hsd-ES]:[5387044] CCB 136410 Add Warnings for any AEP non-POR configs
8.[Hsd-ES]:[5387069] DXE Mailbox Nonce set flow does not check for error condition
9.[Hsd-ES]:[5387217] [PSIRT] PSIRT-BIOS-2017-034: Pull in the solution for "SMM IO Mem Address access issue" to UDK2018 branch
10.[Hsd-ES]:[5387339] [IPS 2204296898] (Purley-R)(Purley) SMI error logging is Incorrectly configured.
11.[Hsd-ES]:[1305855637]Should not trigger NMI for DCPMM DIMM error
12.[Hsd-ES]:[1605946020] Sync PC codebase with RP RAS commits.
13.[Hsd-ES]:[5387218] CCB 136469 AEP ARS SW: Required improvements to ARS to reduce boot time and properly report errors
14.[Hsd-ES]:[5387345] There's a uninitialized variable reference in MicrocodeDetect function () after s5387021 change.
15.[Hsd-ES]:[5387385] [CLX B0 PO] Directory disable knob implementation needs to account for additional register settings as per CCB spec
16.[Hsd-ES]:[2007360181]After CE injection, fault DIMM LED remains asserted despite follow up reset shows healthy memory subsystem - V02
17.[Hsd-ES]:[5387055] Montage found TxV margin degradation on LRDIMMs in current MRC code
18.[Hsd-ES]:[5387312] [Purley-R][CR-2S]NGN_ECC_WR_CHK value shows 0 in serial log after set ECC write check to Enable.
19.[Hsd-ES]:[5387434]PurleySktPkg/MemRas: 2LM BIOS Reverse address translation unable to decode DPA correctly
20.[Hsd-ES]:[5387222][RAS][AD] PMEM bad block offset does not match with error injection block
21.[Hsd-ES]:[5387357]NVDIMM device object _LSI (CLSI) method sometimes returns Buffer rather than Package [IPS 2204324889]
RP release Reference code version: CP_PURLEY_0548_D01.
This release is mapping to RP daily build:CP_PURLEY_0548_D02.		

================================================================================
================================================================================
                               0D.01.0064
================================================================================
1.[Hsd-ES]:[5387391] - False media disable reporting in bios with hang at
 Major=0xf Minor=0x3 after loop1349
2.[Hsd-ES]:[5387224]:WW17 BIOS Stuck in Infinite LOOP while processing CheckForIioErrors after 1008 loops
3.[Hsd-ES]:[5387152]: MRC: Boot time optimization for DDRT configs
4.[Hsd-ES]:[5387430]: [CR] Bios report that provisioning is supported when is unsupported
5.[Hsd-ES]:[5387473]: BIOS should not check the "Die Sparing Capable" bit when detecting the mixed SKU configuration
6.[Hsd-ES]:[5387412]: Enclose the DragonRock AP specific changes and CLX64L CPU specific changes  with "Restricted" tags.
7.[Hsd-ES]:[5387349]: CLONE from skylake_server: Mailbox Error Handling: Delay within SMI code violates SMM rule
RP release Reference code version: CP_PURLEY_0545_D13.
This release is mapping to RP daily build:CP_PURLEY_0546_D06.		

================================================================================
                               0D.01.0062
================================================================================

1.[Hsd-ES]:[2007351139] [Promote.RP] BKC Purley-R - Wrong AEP DIMM information returned by "ApachePassCli.efi show -topology" command on BNP with AEP 2-1-1 configuration.
2.[Hsd-ES]:[2103622826] [Purley_refresh] Boot manager still show pcie device if disable it on PCIe Port Oprom Control.
3.[Hsd-ES]:[5386370] BSSA API must use WrLvlDelay instead of TxDqsDelay + TxDqDelay for WrLvlDelay margin parameter
4.[Hsd-ES]:[5387451] [CR] DFX option for disabling NVDIMM config lock does not work after recent changes
5.[Hsd-ES]:[2103622754] There are no show up "Storage Controller "options with UEFI Option ROM Control page in enable RSTe RAID mode.
6.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3215 from RP
7.[Hsd-ES]:[2103623019]  [Purley_refresh] "DDRT" ECC config show all disabled and cannot be set to enabled.
8.[Hsd-ES]:[2103622550]Package C-state can only enter C1 with all Package C-state mode
9.[Hsd-ES]:[5387225] [CLX B0 PO] CLONE SKX Sighting: [2LM, CR] Supercollider + DDR4 ECC hitting m2m retry hangs
10.[Hsd-ES]:[5387044] CCB 136410 Add Warnings for any AEP non-POR configs
11.[Hsd-ES]:[5387379] NFIT 'NVDIMM Physical ID' and SMBIOS Memory device type 17 'Handle' field are 0 for non-functional dimm
12.[Hsd-ES]:[5387385] [CLX B0 PO] Directory disable knob implementation needs to account for additional register settings as per CCB spec
RP release Reference code version: CP_PURLEY_0545_D13.
This release is mapping to RP daily build:CP_PURLEY_0546_D04.													  
================================================================================
                               0D.01.0048
================================================================================
1.[Hsd-ES]:[5387428] [CLX B0 PO] [1LM] 2DPC 16Gb LRDIMM giving PCU error.
2.[Hsd-ES]:[5386984] CCB 136399 Request to change memory channel disable mechanism in BIOS.
3.[Hsd-ES]:[5387244] [CLX] Disable DBP-F feature by default, expose MSRs to control feature enablement[update].
4.[Hsd-ES]:[2103622551] SUT will trigger IERR after first strike on ADDDC mode with 1-1-1 2LM config..
5.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3207 from RP.
6.[Hsd-ES]:[5387384] [CLX B0 PO] WPQ-Flush M2mem pads not being programmed.
7.[Hsd-ES]:[5387421] [CLX B0 PO] Suspecting that BIOS is not programming the correct min_power values for DRAM RAPL on 2dpc config.
8.[Hsd-ES]:[5387407] BIOS Fix for s5354903 needs to be updated for CAP Mirror Failover case.
9.[Hsd-ES]:[5387322] [PERF][1LM AD & 2LM] Reconcile lower DDR bandwidth with 64G LRDIMM and AEP plugged-in
10.[Hsd-ES]:[5387321] The platform configuration check hasn't detected that interleave set is broken because the DIMM(s) were moved
11.[Hsd-ES]:[5387366] Overwrite NVDIMM DSM call during Overwrite operation returns status 9 (HW Not Ready) instead of 5 (Other Command In Progress)
RP release Reference code version: CP_PURLEY_0545_D03.
This release is mapping to RP daily build:CP_PURLEY_0545_D03.													  
================================================================================
                               0D.01.0041
================================================================================
1.[Hsd-ES]:[2103622742] [Purley-Refresh] Fix DDRT CAP Error report incorrect.
2.[Hsd-ES]:[5387175] CLONE from skylake_server: Some of Pmem Region Missing in Linux after multiple power cycles.
3.[Hsd-ES]:[5387396] [Purley-R][CLX B0 PO] SUT can't boot up when disable lowest bit core under BIOS setting Core Disable Bitmap.
4.[Hsd-ES]:[5387359] Fixed timeout when retrieving nlog using OS mgmt sw.
5.[Hsd-ES]:[5387371] [CLX B0 PO]BIOS not programming the correct ddr4 read weights for DRAM RAPL at 2666Mhz on 111 config with RC16 ddr4 dimms.
6.[Hsd-ES]:[5387282] Klocwork Errors in \CpPlatPkg\Whea\.
7.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3192 from RP.
8.[Hsd-ES]:[5387367] Add additional UBA DXE drivers required for DragonRock Platform template.
9.[Hsd-ES]:[5387038] Add GCC compiler support code for softsku Solution.
10.OSS_0008108  Integrate SPS E5_04_01_02_161_0 to Trunk.
RP release Reference code version: CP_PURLEY_0543_D03.
This release is mapping to RP daily build:CP_PURLEY_0543_D06.													  
================================================================================
                               0D.01.0026
================================================================================
1.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3186 from RP
2.[Hsd-ES]: [5385575] Purley Refresh (CLX) needs to add build support for VS 2015 U3
3.[Hsd-ES]: [5387364] [CLX B0 PO]  Disable Directory 4 App Direct setup option strings needs to be changed
4.[Hsd-ES]: [5386878] [CLX B0 PO] [DDR4] 16Gb 2DPC 3DS LRDIMM TOR TO After MRC complete.
5.[Hsd-ES]: [5387352] [CLX B0 PO] link_cfg_read_1[11] bit removed for B0 PO BIOS
6.[Hsd-ES]: [5386370] MRC: BSSA API must use WrLvlDelay instead of TxDqsDelay + TxDqDelay for WrLvlDelay margin parameter
7.[Hsd-ES]: [5387244] [CLX] Disable DBP-F feature by default, expose MSRs to control feature enablement
8.[Hsd-ES]: [5387348] [1LM] Memicals + DDRT + mirror harasser with failover hangs with DDRT/DDR4 retry fsm both stuck in RD DRAIN state (0xd/0x2) and Patrol FSM hang
9.[Hsd-ES]: [5387343] Align BIOS check of Thermal Throttle Programmability compatibility with first official FIS 1.10 FW
10.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3177 from RP
11.[Hsd-ES]: [1506124820] [Purley PSIRT Factory BMC & BIOS] enabling one-time software update to any version
12.[Hsd-ES]: [2103622512] [BMP] NIC devices disappear in Boot Manager when installed OCP module.
RP release Reference code version: CP_PURLEY_0543_D03.
This release is mapping to RP daily build:CP_PURLEY_0543_D06.													  
================================================================================
                               0D.01.0010
================================================================================
1.FIV8109/8110 Update BIOSACM/SINIT 1.6.4
2.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3168 from RP
3.OSS_0008108 Integrate SPS E5_04_01_02_161_0 to Trunk
4.[Hsd-ES]: [2202640819] System will not boot to IPV4 PXE if UEFI Network Stack disabled for IPV6 PXE in BIOS
Reference code version: CP_PURLEY_0541_D12.
This release is mapping to RP release:CP_PURLEY_0541_D12.
================================================================================
                               0D.01.0002
================================================================================
1.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3149 from RP
2.OSS_0008036: Integrate Microcode 0200004d for SKX H0 from PC-Purley Skylake
3.OSS_0008038: Integrate Microcode 01000144 for SKX B1 from PC-Purley Skylake
4.[Hsd-ES]: [1605354891] TPM Update fail on STP and WFP
5.[Hsd-ES]: [2103622392] AEP DIMM Status is not displayed under Memory Configuration Setup Page.
6.[Hsd-ES]: [2103621831] Intel XXV710 card often not be detected when DC cycling.(FR:70%)-V01
Reference code version: CP_PURLEY_0541_D04.
This release is mapping to RP release:CP_PURLEY_0541_D04.
================================================================================
                               01.00.0918
================================================================================
1.FIV7191 ME_SPS_E5_04.01.00.119.0 Config file change request
2.Integrate Microcode 0300000d for CLX A0
3.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3135 from RP
4.[HSD-ES] [1505083055] BIOS support for WFC, WFD, WFS cluster systems
5.[HSD-ES] [1506122246] Sync RP RAS fix to PC RAS code - 5372870: CCB 135686 Customer visible error injection hooks beyond FIS 1.2.
Reference code version: CP_PURLEY_0540_D02.
This release is mapping to RP release:CP_PURLEY_0540_D02.
================================================================================
                               01.00.0907
================================================================================
1.[PC Stitching] Update RSTeSataEfi version to 6.0.0.1006 for RP
2.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3129 from RP
3.[Hsd-ES]: [1506122199] Sync RP RAS fix to PC RAS code - 5386479: CCB 136242 [CR] DSM SMM to ASL migration, phase 2 (Query ARS Status, disabling error injection on ASL layer).
4.[Hsd-ES]: [2103621945]  Windows2016 cannot be installed with SATA port5+port7 RSTe RAID0
5.[Hsd-ES]: [2103622371]  [BMP] There's no PCIe error SEL log when inject PCIe error via ITP.
6.[Hsd-ES]: FIV7828 Update BIOSACM/SINIT 1.6.3
7.[Hsd-ES]: [5386515] PeiDxeSmmPchSerialIoLib.c should be removed from Dsc file
8.OSS_0007902 Integrate Intel Apache Pass UEFI driver v01.00.00.3129 to Trunk
9.OSS_0007054  OSS_0007054: Integrate Microcode 01000142 for SKX B1 from Purley Skylake
10.OSS_0007040: Integrate Microcode 02000049 for SKX H0 form Purley Skylake
11.OSS_0007824 Update RSTeSataEfi version to 6.0.0.1006 for RP
Reference code version: CP_PURLEY_0539_D01.
This release is mapping to RP release:CP_PURLEY_0539_D01.
================================================================================
                               01.00.0895
================================================================================
1.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3102 from RP
2.[Hsd-ES]: [2103622005] Bit[3:0] of MSR 0xE2 is always 0x2 after change package C-state with CLX CPU
3.[Hsd-ES]: [1504784817] CCB2267[Purley BMC+BIOS]Need mechanism for BMC to return MAC addresses for add-in card on demand
4.[Hsd-ES]: [2204043771] BMP SKX-P - PKG RAPL register left permanently LOCKed.need to only lock power limit csr registers
5.[Hsd-ES]: [2006662617] Fix TXT can't be enabled on Blue Mountain Pass Board
6.[Hsd-ES]: [1506111792] RAS- Rollback the changes of HSD 2103620947.
7.[Hsd-ES]: [1506113185] Purley PC RAS - Skip AEP DIMM for ADDDC action.
8.[Hsd-ES]: [1506113181] Sync RP RAS fix to PC RAS code - 5386689 [CLX A0 PO] CLONE SKX Sighting: [promoted] [Beta gating] System hangs when consuming poison data from far memory
9.[Hsd-ES]: [1506113206] Purley PC RAS - remove duplicate 2LM mode judgement interface.
10.[Hsd-ES]: [1506112341] Sync RP RAS fix to PC RAS code - 5386668 [CLX A0 PO] CLONE from skylake_server: cfgmcacorrondatauc register needs to be cleared when poison is enabled
11.[Hsd-ES]: [1506112659] Sync RP RAS fix to PC RAS code - -5386275: [CLX A0 VV] 2LM 222,211 2MC ADDDC UC Error During Sparing
12.[Hsd-ES]: [1506112852] Sync RP RAS fix to PC RAS code - 5386568: [CLX PO] retry_rd_err_log_address1 reporting incorrect rank (Changes need to be extended for CLX)
13.[Hsd-ES]: [2006995749] SUT continues fully responsive after several NMI events - V02
14.OSS_0007794  OSS_0007794 Integrate SPS E5_04_01_00_144_0 to Trunk
15.OSS_0007796  OSS_0007796 Integrate Intel Apache Pass UEFI driver v01.00.00.3102 from RP
Reference code version: CP_PURLEY_0537_D07.
This release is mapping to RP release:CP_PURLEY_0537_D07.
================================================================================
                               01.00.0887
================================================================================
1.OSS_0007713 Integrate Intel Apache Pass UEFI driver v01.00.00.3086 to Trunk
2.[Hsd-ES]: [1506112561] Sync RP RAS fix to PC RAS code - 5385908: Programming changes needed for 3CH 2LM sparing
3.[Hsd-ES]: [1506112531] Sync RP RAS fix to PC RAS code - 5385980: ADDDC initiated by error injection causes uncorrectable error
4.[Hsd-ES]: [1506112490] Sync RP RAS fix to PC RAS code - 5386772[CLX A0 PO] CLONE from skylake_server: IsolateFaultyDimm fails with error in TranslateDDRTTad(CL576341)
5.[Hsd-ES]: [1506112074] Sync RP RAS fix to PC RAS code - 5386568: [CLX PO]  Need to extend the changes in 5372419 for CLX.
6.[Hsd-ES]: [1506112322] PC RAS -sync cfgmcasmioncorr with CRB.
7.[Hsd-ES]: [1506112046] Sync RP RAS fix to PC RAS code - 5385535: Cloned From SKX Si Bug Eco: <H0> [*DDC] Failures when Injecting During Sparing  (CL494421 & CL495495).
8.[Hsd-ES]: [1506111822] Sync RP RAS fix to PC RAS code - 5385610: Address translation isnt building CS correctly (CL506859).
9.[Hsd-ES]: [1504597391] UCE Non-fatal memory error can't be injected to DDR4 via WHEAHCT tool.
10.[Hsd-ES]: [1506112343] Sync RP RAS fix to PC RAS code - [5386205] MSMI handler doesnt comprehend DDRT link errors.
11.[Hsd-ES]: [1506110703] Sync RP RAS fix to PC RAS code - 5385252: Storm of SMI in SVLS config.
12.[Hsd-ES]: [1506111273] Sync RP RAS fix to PC RAS code - 5372957: CLONE SKX Sighting: (CR) 2LM mode: Memicals DataCorruption during Rank Spraring Event.
13.[Hsd-ES]: [1605106640] Purley PC PCIE AER-Don't Log the error that already masked in SEL
14.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3086 from RP
Reference code version: CP_PURLEY_0536_D12.
This release is mapping to RP release:CP_PURLEY_0536_D12.
================================================================================
                               01.00.0877
================================================================================
1.OSS_0007635:  Integrate SPS E5_04_01_00_140_0 to Trunk
2.[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3078 from RP
3.[Hsd-ES][1505955731]RP PCIE Unsupported Request Related sightings:5386950 5372426 and 5385246
4.[Hsd-ES][1505889856]update CreatePcieErrorRecord() function which capture the failed device Bus number.
Reference code version: CP_PURLEY_0536_D02.
This release is mapping to RP release:CP_PURLEY_0536_D02.
================================================================================
                               01.00.0866
================================================================================
[HSD-ES] [1505889856] update CreatePcieErrorRecord() function which capture the failed device Bus number.
[HSD-ES] [1505866814] Sync RP RAS code change for sighting 5386679 and 5386045
[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3069 from RP
[HSD-ES] [1504707008] Add Infineon FW update capability support in BIOS
Reference code version: CP_PURLEY_0534_D09.
This release is mapping to RP release:CP_PURLEY_0534_D12.					   						   
================================================================================
                               01.00.0856
================================================================================
BIOS POST messaging shows no errors when in fact a DIMM is mapped out
OSS_0007438 Integrate CLX A0 ucode mb750655_0300000b to Trunk
[HSD-ES][1505330637] add two APIs in fast video ppi and protocol
OSS_0007439 [PC Stitching] Sync CLX A0 Microcode 0x0300000b from RP
FIV7455 Update SKX B1/H0 stepping ucode ingredients
[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3053 from RP
Reference code version: CP_PURLEY_0534_D02.
This release is mapping to RP release:CP_PURLEY_0534_D02.
================================================================================
                               01.00.0842
================================================================================
[HSD-ES][1504765250] Purley_refresh failed to power on with daily build debug bios from D0787
Reference code version: CP_PURLEY_533_D08.
This release is mapping to RP release: CP_PURLEY_533_D08.
================================================================================
                               01.00.0833
================================================================================
OSS_0007270[PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3019 from RP
[HSD-ES][2103620906] Boot to primary bios will cause system hang on 0x9A when corrupted BB backup region 0x3e70000
Reference code version: CP_PURLEY_532_D13.
This release is mapping to RP release: CP_PURLEY_532_D13.
================================================================================
                               01.00.0824
================================================================================
[HSD-ES][ 1504771459] [Purley] After clear CMOS, EWS doesnˇŻt display about CMOS log when boot to BIOS setup.
Reference code version: CP_PURLEY_532_D04.
This release is mapping to RP release: CP_PURLEY_532_D04.
================================================================================
                               01.00.0821
================================================================================
[HSD][587233] Update the WFP ACPI Slit table to populate the slit distance
[HSD-ES][2202507580] Create Purley refresh BIOS release to support Buchanan Pass
[HSD-ES][2103621559] BMC status is unknown with 84F2 error after set CMOS jumper
[HSD-ES] [150476246] Add option to configure fan pwm offset in syscfg  on Purley.
[HSD][5386926] Revert - "DWR knob default value changed as enabled"
OSS_0007178 [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.3000 from RP
[HSD-ES][1504771008] Removing the spaces in PC: Restricted TAG
Reference code version: CP_PURLEY_532_D01.
This release is mapping to RP release: CP_PURLEY_531_D02.
================================================================================
                               01.00.0797
================================================================================
[HSD-ES][1504749852] Add SMBIOS OEM String modification capability in ITK
[HSD-ES][2103620480] [BMP] There are some BIOS Setup UI relate issues with EPS1.07
221360: Fix the Microcode missing in FIT table issue
OSS_6999: [PC Stitching] Update RSTE Drivers to version 5.4.0.1039
OSS_0007034: PurleyPcPkg/NvmDimmDriver: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2032 from RP
[HSD_ES][1504719238] Request to remove all knobs overrides on WFFR
[HSD_ES][2202309233] Wolfpass BIOS default non-user EV DFx setting prevents CScripts from accessing AEP modules
[HSD-ES] [2103621261 [WFP]SMBIOS Type 8 NIC number is not match motherboard number.
[HSD-ES][2103620931] [BMP] Boot to primary bios will cause system hang on 0x9A when corrupted BB backup region 0x3e70000
[HSD-ES]1504690886:[BMP]BIOS D0705 Online update fail
Reference code version: CP_PURLEY_529_D02.
This release is mapping to RP release: 20180326_CP_PURLEY_528_D06.
================================================================================
                               01.00.0783
================================================================================
OSS_0006979: [PC Stitching] Sync CLX A0 Microcode 0x03000009 from RP
Reference code version: 20180315_CP_PURLEY_527_D05.
This release is mapping to RP release: 20180315_CP_PURLEY_527_D05.
================================================================================
                               01.00.0781
================================================================================
5386472: CCB 136242 [CR] DSM SMM to ASL migration, phase 1 (Vendor-Specific commands minus large payload commands)
OSS_0006927 [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2028 from RP
Reference code version: 20180313_CP_PURLEY_527_D03.
This release is mapping to RP release: 20180313_CP_PURLEY_527_D02.
================================================================================
                               01.00.0777
================================================================================
[HSD-ES][1504746104] Remove unsupported BIOS guard feature to save the FV Main space for PC BIOS.
[HSD-ES][2103621073] [BMP] Boot order list is not matched between F9 and syscfg / bldfs
219740 [PC Stitching] Update ME SPS version to MR 313
OSS_0006872 [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2023 from RP
OSS_0006871 [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2018 from RP
5386585: CCB AEP2_CR 2LM PERF - Add ACPI HMAT table for Windows & Linux cache coloring 2LM Performance improvements
[HSD-ES][2103620947] The SBE location is incorrect in SEL after inject SBE to AEP with 2-2-2 2LM config.
[HSD-ES][2103620831] System has beep code 1-5-1-2 and 1-5-4-4 when auto power on with first Programmer BIOS.
Reference code version: 20180311_CP_PURLEY_526_D59.
This release is mapping to RP release: 20180306_CP_PURLEY_526_D56.
================================================================================
                               01.00.0762
================================================================================
None.
Reference code version: 20180222_CP_PURLEY_526_D46.
This release is mapping to RP release: 20180222_CP_PURLEY_526_D46.
================================================================================
                               01.00.0761
================================================================================
OSS_0006747: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2016 from RP
573658: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2005 from RP
[HSD-ES][1504707003] Q1'18 #CCB1822 [ Purley BIOS-Post Launch]Support Relax Ordering and No Snoop in BIOS setup and ITK
Reference code version: 20180220_CP_PURLEY_526_D43.
This release is mapping to RP release: 20180220_CP_PURLEY_526_D43.
================================================================================
                               01.00.0751
================================================================================
OSS_0006679: Integrate CLX A0 ucode mb750655_83000006 to Trunk
[HSD-ES][1504630755][Purley] Change "CPU Power and Performance Policy" from "Balanced Performance" to "Performance" on the custom BIOS capsule by ITK tool, related items "C1E" can?t be changed automatically
[HSD-ES][2103621061][Purley][STP] BIOS copyright information 2006-2017 should be changed to 2006-2018
OSS_0006635: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2002 from RP
HSD_ES[2103620830] Display always show black screen when install M6000 VGA card in Both socket under UEFI mode.
Reference code version: 20180208_CP_PURLEY_526_D29.
This release is mapping to RP release: 20180206_CP_PURLEY_526_D25.
================================================================================
                               01.00.0744
================================================================================
OSS_0006634: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.2000 from RP
OSS_0006633: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1997 from RP
[2103621067][BMP] The mirror mode items duplicate in ITK.
[HSD-ES]1504716887: Debug message has name on it
Reference code version: 20180204_CP_PURLEY_526_D21.
This release is mapping to RP release: 20180201_CP_PURLEY_526_D18.
================================================================================
                               01.00.0735
================================================================================
[HSD-ES] 2103620835 APCI TPM2 table info doesn't match test case.
[HSD-ES] 2103620805 'Total DDR4 Memory' size include AEP DIMM size with 1LM/2LM mode.
[HSD-ES]1504651973: The SerialA Console continues to work while the VGA screen appears hung after enable serial port A enable and input "reconnect -r" in efi shell ,update Aspeed GOP to v1.07.
[HSD-ES]1504690886:[BMP]BIOS D0705 Online update fail.
[HSD-ES]:2103620843 [BMP] BMP does not support NTB function, the NTB option is not hidden.
HSD_ES[2103620812] MMIO size set to Auto / 1G can?t boot to BIOS with NIC Card-XL710 in Legacy mode.
HSD_ES[2201740540] WFFR bios 0691 not following DFT rule 1629 for comport redirection.
OSS_0006532: Integrate CLX A0 ucode mb750655_83000003 to Trunk.
OSS_0006528: Integrate SPS E5_04_01_00_108_0 to Trunk.
OSS_0006496: Integration of CLX A0 Microcode patch v0x83000002 to Trunk.
[HSD-ES]2103620739: [BMP] If the EFI Shell in first boot option, exit will fail to the BIOS setup after EFI Shell booting.
[HSD-ES] 2103620771 [BMP] PCIe Slot Bifurcation Setting and PCIe Error Maintain items are blank in BMP BIOS UI.
HSD ES [2103620753] SUT can not boot correctly after create goal with memory mode = 50% on 2LM 2-2-2 config.
[HSD-ES]2103620760:[BMP][D0709] Entering BIOS setup/Boot manager/press F9 system will run some garbage info with NVMe SSD.
[HSD-ES] 1504705784 [PC Stitching] Integrate the OPA UEFI driver v1.6.0.0.0 from RP.
OSS_0006460: Integration of Microcode patch v0x3F for SKX H0 (Trunk).
Reference code version: 20180126_CP_PURLEY_526_D11.
This release is mapping to RP release: 20180123_CP_PURLEY_526_D07.
================================================================================
                               01.00.0722
================================================================================
[HSD-ES]2103620695: BIOS cannot upgrade/downgrade between D702 and D709.
[HSD-ES]2103620717 [BMP] - Attempt Secure boot option can't set to Enable in the BIOS Setup UI.
[HSD-ES] 1504696215: #CCB2216: [CLX-R]Enable HTTPS Boot on Purley Refresh BIOS.
OSS_0006403:  Integration CLX A0 PO microcode patch.
OSS_0006402: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1989 from RP.
[HSD-ES] 2103620708 'Resume on AC Power Loss' option default value is different between CMOS and F9.
[HSD-ES] 2103620756 Smbios Type 9 Slot Type is incorrect when use triple slot riser.
[HSD-ES]1504686401: Integration BIOS ACM to 1.3.4.
OSS_0006382:  Integration Intel Apache Pass UEFI driver 01.00.00.1989.
[HSD-ES] /1504695154: D-base code optimization for using PCD to reduce times of getting Board SKU and OCP FRU.
Reference code version: 20180109_CP_PURLEY_525_D11.
This release is mapping to RP release: 20180109_CP_PURLEY_525_D10.
================================================================================
                               01.00.0715
================================================================================
[HSD-ES]1504629477: #CCB2119: [CLX-R]Enable HTTP Boot on Purley Refresh BIOS
Reference code version: 20180106_CP_PURLEY_525_D03.
================================================================================
                               01.00.0709
================================================================================
HSD ES[1504687181] [AEP WFP] CkeProgramming, PpdEn, DdrtCkeEn, and OppSrefEn knobs are no longer needed to boot CR systems.
[HSD-ES]2103619028:[BMP] UEFI default boot order is incorrect after load default at BIOS D0605 ?? About PXE and HTTP Boot Order.
[HSD-ES][1504690886]: [BMP]BIOS D0705 Online update fail (Addendum to CL#561576).
HSD ES [2103620379] Type 9 Riser3 slot1 Slot Type is incorrect.
HSD ES[2103620383] After disable PCIe Port 1a OpROM control , PCIe Port 3a OpROM control will disable at the same time in ITK.
[HSD-ES] 1504691258 [PC Stitching] Remove SKX A1/B0  Microcode support for CR.
[HSD-ES]1504686401: Integration BIOS ACM to 1.3.4.
OSS_0006116:  Fort Park NVM 3.51 image with new OROM to be included in IFWI for Purley 2S.
[HSD-ES]1504690886:[BMP]BIOS D0705 Online update fail.
OSS_0006117: Integration of Fort Park signed NVM 3.51_80000F2B for Purley 4S.
OSS_0006105: Integration of SPS vE5_04_01_03_099_0 (Trunk).
Reference code version: 20171228_CP_PURLEY_524_D29.
================================================================================
                               01.00.0703
================================================================================
OSS_0006075: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1984 from RP 
Reference code version: 20171217_CP_PURLEY_524_D18.
================================================================================
                               01.00.0702
================================================================================
OSS_0006070: Integration Intel Apache Pass UEFI driver 01.00.00.1984 
OSS_0006062: [PC Stitching]Update ME SPS version to MR 309
OSS_0006029: [PC Stitching] Sync Microcode 0x3c for SKX H0 from RP
OSS_0006033: Integration of Microcode patch v0x3c (Trunk)
Reference code version: 20171215_CP_PURLEY_524_D17.
================================================================================
                               01.00.0698
================================================================================
OSS_0006009: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1982 from RP 
OSS_00006008:  Integration Intel Apache Pass UEFI driver 01.00.00.1982
[HSD-ES]1504680515:[CCB 2076]  Allow user to change serial communications setting values independent of Console Redirection and Serial Over LAN state
[HSD-ES]1504626593:[BNP]Some variables cannot load default when it was deleted after SUT reset
[HSD-ES]1504619685 [AEP WFP] System hang at 0x94 after Enable TXT with bios D0643.
[HSD-ES] 2103620185 [BMP] Sub-NUMA is gray out in Setup after install DIMM on each iMC with FPGA CPU.
Reference code version: 20171210_CP_PURLEY_524_D11.
================================================================================
                               01.00.0694
================================================================================
OSS_0005965: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1978 from RP 
NO HSD. [WFFR] Need to add IFWI ingredient table for CR build.
OSS_0005962: Integration of SPS vE5_04.00.04.309 (Trunk)
OSS_00005701: Intergation Intel Apache Pass UEFI driver 01.00.00.1978
Reference code version: 20171205_CP_PURLEY_524_D04.
================================================================================
                               01.00.0692
================================================================================
None.
Reference code version: 20171201_CP_PURLEY_523_D25.
================================================================================
                               01.00.0691
================================================================================
HSD_ES 2103620100 [WFFR] After removing QAT cable the SATA controller is still disabled.
HSD_ES 2103620140 [WFFR] Smbios Type 8 doesn't list table of CPU1 PCIe_SSD and  SATA port connector
Reference code version: 20171130_CP_PURLEY_523_D23.
================================================================================
                               01.00.0686
================================================================================
[HSD-ES] 2103616135 [BMP]SUT will halt at 0xEE with DIMM attached on CPU1_A1 and CPU2_A1 and NUMA disabled.
[HSD-ES]2103619690][BMP] Populate all PCIE slots with storage cards in recovery mode, the SUT will reboot loop after post code 0x94
[HSD-ES][2103619922: [WFP] Smbios Type 8 doesn't list table of CPU1 PCIe_SSD port connector on WFQ.]
[HSD-ES]1504659011: update RTK usb driver to V2.021,  Q4 SW stack need integrate  latest v2.021R8153 EFI driver
[HSD-ES] [1504653444:[BNP] ITK modified Bifurcation settings for Riser slots will revert back to factory default value after pressing f9.]
HSD-ES 2103619444 [WFP] Lan Device will disappear if only enable one NIC port after two NIC ports both are disabled.
OSS_0004637: Integration of Microcode patch v0x38 (Trunk)
[HSD-ES] 1504657333 [BMP] expose "HSSI EQ Manual Tuning" and "DXE unlock" setup option to "Hardware Validation Test Only" setup page 
[HSD-ES] 2006663518 :STP QAT SKU PCH PCIE Uplink margin failed on Silver Build 3(PCH=QN1L B2)
OSS_0003892: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1970 from RP
OSS_0003890: Integrate Intel Apache Pass UEFI driver 01.00.00.1970
[HSD-ES]2103619513:[WFFR] Casecade 4 port OCP only show 2 MAC address at NIC configuration page
[HSD-ES]2103619650:[BMP]Boot order is not changed in MFG mode after use command "syscfg /bbo" to change it.
Reference code version: 20171130_CP_PURLEY_523_D23.
================================================================================
                               01.00.0674
================================================================================
OSS_0003875: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1968 from RP
OSS_0002062: Integrate Intel Apache Pass UEFI driver 01.00.00.1968
[HSD-ES]: 2006676137: [STP] BIOS F2 menu doesn't show drive's OPROM under re-timer AIC in slot 4 when populating slot 2 with RSP3WD080.
Reference code version: 20171114_CP_PURLEY_523_D04.
================================================================================
                               01.00.0665
================================================================================
OSS_0002060: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1962 from RP.
[HSD-ES]1504644929 : [BMP][D0654][issue]SUT will halt at 0x96 when boot to D0654 MBIST BIOS in MFG mode.
[HSD-ES] 2103619292 : C1E help text character display abnormal under console redirection.
[HSD-ES] 2006677577 : Unable to locate/fault/rebuild instructions to NVME drive  from EFI tool and OS for drives  under retimer AIC.
[HSD-ES 2103619519 [WFFR] &#8216;Intel PCH Integrated 10 Gigabit Ethernet Controller' is NOT listed in SMBIOS Type41.
[HSD-ES][Purley] [ 2103617706 : [Retimer]The system HDD5~7 carrier LED no display on first power on.
[HSD-ES] 2103619456 : [BNP] the Current Usage of SMBIOS Type 9 - System Slots are all In use even no PCIe Device attached with -F CPU.
OSS_0002056: [PC Stitching] Update ME SPS version to MR 294.
OSS_0002055: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1957 from RP.
[HSD-ES] 1604527341 : CLONE from bios_purley: [HaT] 3rd party code (OPROMs) can fake their TPM measurement
HSD-ES[ 2103619504 ] WFFR] PCIe Port Oprom Control page shows wrong information. 
Reference code version: 20171106_CP_PURLEY_522_D09.
================================================================================
                               01.00.0655
================================================================================
OSS_0002045: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1955 from RP.
[HSD-ES] 1504591223 [Cray]Iflash32 utility can't get ITK modified custom BIOS revision string correctly.
OSS_2043: [PC Stitching] Sync SKX B1 Production Patch 0x13d from RP.
OSS_0002041:[PC Stitching] Sync Microcode 0x35 for SKX H0 from RP.
OSS_2036: [PC Stitching] Update RSTE Drivers to version 5.3.0.1052.
[HSD-ES] 1504626704 : [WFFR][D0650] SUT will reboot loop after running updateAll.nsh in current BIOS when disable NIC Controller.
[HSD-ES] 1504620840 : [BNP] CHIPSEC test find all PRx set to 0 after enable security.
[HSD-ES] 1504596343 [BMP] BIOS Alaska Card support.
[HSD-ES] 2103619297 [BNP] ME status shows ˇ°Not readyˇ± and ME revision shows ˇ°Unknown" after SPS FW  online downgrade from 04.00.04.285 to 04.00.03.235.
[HSD-ES] 2103619177 : [WFFR] Boot time becomes very slowly, almost 6 times after flash FTPM Enabled Capsule file on IPCR BIOS D0621.
[HSD-ES] 1504624642 : [AEP WFP]Remove unused RsaInit driver for AEP BIOS.
[HSD-ES]1504626226 : [WFFR] SFID for the WFFR bin is none, that should be porting by BIOS Dev.
Reference code version: 20171024_CP_PURLEY_521_D21.
================================================================================
                               01.00.0649
================================================================================
OSS_0002033: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1953 from RP.
[HSD-ES] 1504624642 : [AEP WFP]Remove unused RsaInit driver for AEP BIOS.
[HSD-ES] 1504622459 : sync skylake_pc_production cl528422 to skylake_trunk remove xpt prefetch setup option.
[HSD-ES] 1504619524 : code sync for RP sighting 5370446 UncEdMask.Bits.poisoned_tlp_detect_mask.
[HSD-ES] 2103619114 : [WFP] Modify Legacy Boot Order "EFI Shell" item via ITK do not take effect, shell always in the Bottom.
[HSD-ES] 2103619105 : BIOS D594 not boot first to EFI shell in manufacture mode.
[HSD-ES] 1504618752 Fix CL540878 Klocwork issue.
OSS_0002025: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1950 from RP.
Reference code version: 20171016_CP_PURLEY_520_D07.
================================================================================
                               01.00.0643
================================================================================
OSS_0002023: [PC Stitching]Update ME SPS version to MR 288.
[HSD-ES] 1504581583 Rp RAS code sync  CL528211  5386077: SKX Mirrorfailover should happen when mirrorfailover=1 and (mccmdvld=1 or errortype[4]=1).
[HSD-ES]2103619153 - [BMP]The OCP device list in SMBIOS type 41 structure not match with WFP WFQ/WF0 SKU.
[HSD-ES]1604353738 [CR on Cluster] BIOS Support Needed for Knob changes in automation.
OSS_0002021: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1944 from RP.
OSS_0002017:[PC Stitching] Sync Microcode 0x32 for SKX H0 from RP.
OSS_0002012: [PC Stitching] BBS Package 6.4.0 for IFWI integration.
Reference code version: 20171009_CP_PURLEY_519_D22.
================================================================================
                               01.00.0632
================================================================================
[HSD-ES] 2006677946 [BMP] Support to mix FPGA CPU and SKX CPU on BMP platforms.
OSS_0002007: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1938 from RP.
[HSD-ES]2006678011 [BMP] RC_EN signals are not behaving as expected.
OSS_0002006:[PC Stitching] Sync Microcode 0x30 for SKX H0 from RP.
[HSD-ES] 1504599235 [PC Stitching] Sync Microcode 0x30 for SKX H0 from RP.
[HSD-ES] 2103619090 : [BMP] The HEST,BERT,ERST,EINJ table still exist in ACPI table if WHEA is disabled.
[HSD-ES] 1504581854 [AEP] BIOS default value will be changed after online flash BIOS D0610.
[HSD-ES]  1504597970 : Fix Klocwork issue- Array OCPDID Index Out of Bounds.
Reference code version: 20170926_CP_PURLEY_518_D16.
================================================================================
                               01.00.0627
================================================================================
[HSD-ES]1504595887: [BMP] User Configuration in BIOS setup should not to get channel 1 information for default.
[HSDES 1504593655 ] [BMP]"syscfg /lc 1 C7 TestDHCPHostName" will show "TestDHCPHostNamel" in BIOS Setup.
OSS_0002002: [PC Stitching] Sync Intel Apache Pass UEFI driver v01_00_00_1930 from RP.
[HSD-ES] 1504579741 : Q3'17 #CCB 2030: [Purley BIOS/Azure Stack] Enable/disable individual NIC ports.
[HSD-ES]2103618468 : [BNP] Current Active Processor Cores do not show the corresponding number when Active Processor Cores changed with Quad core QMRN CPU.
[HSD-ES][ 1504591221 ] RSD SMBIOS table was overwritten by OOB RSD SMBIOS table.
OSS_0001998: [PC Stitching] Sync Intel Apache Pass UEFI driver v01.00.00.1925 from RP.
[HSD-ES] 1504591154 [BMP]Need sync RP code for fix bug 5385789.
[HSD-ES] 1504589353   [PC Stitching] Sync Microcode 0x2e for SKX H0 from RP.
[HSD-ES] 1504589414: [AEP WFP]Remove unused Matrox video driver for AEP BIOS.
[HSD-ES]2103618637: [BNP] SKU SFP+/1G: UUT show "Nmi activated - system halted" during POST when PCIE riser 2 x8 slot 2 installed a NIC/RAID card.
[HSD-ES] #2103618878 - [BMP] SMBIOS Type 9 is incorrect about "Slot Type" for Riser 3 slot 1.
[HSD-ES][2103618733: [WFP] SMBIOS Type 16 of maximum capacity value of 0x90000000, is not represented in the Extended Maximum Capacity field.
Reference code version: 20170920_CP_PURLEY_517_D26.
================================================================================
                               01.00.0612
================================================================================
[HSD-ES] 1504580786 [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1917 from RP.
[HSD-ES] 220680356   X722 NVM v3.49 BIOS integration.
[HSD-ES] 1504580965 : RsaReadyToBoot should run before AssertPostGpio in ReadToBootEvent.
Reference code version: 20170905_CP_PURLEY_516_D06.
================================================================================
                               01.00.0610
================================================================================
[HSD-ES] 1504581372 : [AEP WFP] System Information show wrong value in BIOS setup UI on BIOS 608.
[HSD-ES] 2103617774 : [BNP] Package C1 always >90% whatever Package C-state with BIOS X0008.
[HSD-ES] 1504580786 : [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1917 from RP.
[HSD-ES] 1504580069 : [PC Stitching] Sync SKX B1 Production Patch 0x13b from RP.
[HSD-ES] 1504580058 : [PC Stitching] Sync Microcode 0x2c for SKX H0 from RP.
[HSD-ES] 1504574989 : [PC Stitching] Sync VMDVROC Driver v5.2.0.1023 with Purley.
[HSD-ES] 1504575089 : remove usb video and usb nic driver.
[HSD-ES] 2103618307 : [BMP] System Boot Timeout function not working if enable Power On Password.
[HSD-ES] 1504573584 : [PC Stitching] Sync SKX B1 Microcode 0x13a with Purley.
[HSD-ES] 1604427104 : Q3'17 #CCB 1952: Lacks of memory thermal management BIOS options on Purley.
Reference code version: 20170831_CP_PURLEY_516_D01.
================================================================================
                               01.00.0605
================================================================================
[HSD-ES] 1504572736  [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1914 from RP.
[HSD-ES] 220675501: Move knob changes to PlatformSetupVariableSyncLib.c.
[HSD-ES] 2103618342   [BMP] Need remove sSATA/SATA onboard RAID in BIOS Setup page.
[HSD-ES] 103617670 : [BMP] The PCI slot capabilities register is not matching between physical slot number, SMBIOS and BIOS UI with FPGA.
[HSD-ES] None Code sync for RasPkg:HSD5385747: CCB 135944 AEP1_CR Interface Standardization - ACPI 6.2 Updates - PHASE 1: Label Consumption via _LSI, _LSR 
[HSD-ES] 1504559251 [PC-Stitching]Update ME SPS version to MR 235.
[HSD-ES] 1504569407 [AEP] "AttemptFastBoot" default setting is removed from RP BIOS.
[HSD-ES] 1504563070 CCB#1896(Part 1):   Provide SMBIOS table type 190 for RSD 2.2 Spec.
[HSD-ES] 1504555611 : [AEP] BIOS default valus has updated in RP BIOS.
Reference code version: 20170822_CP_PURLEY_514_D14.
================================================================================
                               01.00.0599
================================================================================
[HSD-ES] 1504567494 [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1909 from RP.
[HSD-ES] 220641900 Expose Throttling Mode in Wolf Pass BIOS.
[HSD-ES] 1504567160 [WFP]Hard code the variable value of  Processor MSR Lock Control.
[HSD-ES] 2103618046 [BMP] After injecting MBIST error at rank sparing mode, memory size shows wrong.
10nm Sync for HSD0220544630: BIOS is not enabling LMCE (Bit 20 of optin_feature_control ).
[HSD-ES] 504430000 [BMP]NIC PXE is still showed in boot order after disable onboard NIC controller in Setup with UEFI mode.
[HSD-ES] 2103618307  [BMP] System Boot Timeout function not working if enable Power On Password.
[HSD-ES] 1504565295  [PC Stitching] Sync Microcode 0x2b for SKX H0 from RP.
[HSD-ES] 2103618243  [STP] X0038 has an new item "Diagnostic Messages" which should be invisible in BIOS setup.
[HSD-ES] 2103617172 [BNP]UEFI Mode,Boot order value doesn't follow ITKs' with FDD device.
[HSD-ES] 220562642  Update Purley ERST2 UEFI HII code to 05120000.
Reference code version: 20170815_CP_PURLEY_513_D13.
================================================================================
                               01.00.0592
================================================================================
[HSD-ES] 1504558128 [AEP WFP] Warning message pops up when change and save Secure Boot value under BIOS.
[HSD-ES] 1504559603 [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1908 from RP.
[HSD-ES] 2103616704 [BMP] BIOS D0485 can change boot mode to Legacy.
Reference code version: 20170808_CP_PURLEY_512_D09.
================================================================================
                               01.00.0588
================================================================================
[HSD-ES] 1504555611: [AEP] BIOS default valus has updated in RP BIOS.
[hsd-es] 2103618185: [WFP] The memory info will show 'Empty/NO DIMM' in SMBIOS Type 17 if populate 1R DIMM on CPU1 Channel A and B and build Rank Sparing mode.
[HSD-ES] 1504527464: [BMP]"Video BIOS" can be dumped via sysinfo&syscfg when secure boot is enable on Windows2016X64_UEFI.
[HSD-ES] 1504553904: [BMP] Should display BBS version as user readable string.
[HSD-ES] 1504552536: [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1904 from RP.
[HSD-ES] 1504549582: Integration BIOS ACM to 1.3.3.
[HSD-ES] 1504551789: [PC Stitching] Sync SKX B1 Production Patch 0x13a from RP.
[HSD-ES] 1504551442: [PC Stitching] Sync Microcode 0x29 for SKX H0 from RP.
[HSD-ES] 2103617494:  [BMP] SUT will hang in shell and BSOD in windows after remove PCIE SSD from onboard Oculink.
[HSD-ES] 2103617907: [BMP] sSATA Controller page is incorrect.
[HSD-ES] 2103617494: [BMP] SUT will hang in shell and BSOD in windows after remove PCIE SSD from onboard Oculink.
[HSD-ES] 2103617963: [BMP]SMBIOS Type 41 is incorrect after attach SAS module.
[HSD-ES] 220203024: [WFP Retimer] VMD menus do not match system state  (for example 3 slot riser + 4P/8P switch + VROC key + VMD enabled does not enable VROC OpROM in some cases).
[HSD-ES] 1504544598: [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1902 from RP.
[HSD-ES] 2006649255: BKC AEP - Warning event: POST Err Sensor reports CPU1_DIMM_A1 failed test/initialization during reboot. 
Reference code version: 20170802_CP_PURLEY_511_D12.
================================================================================
                               01.00.0580
================================================================================
[HSD-ES] 1504544598 [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1902 from RP.
[HSD-ES] 1504543699 [PC Stitching] Sync SKX B1 Production Patch 0x139 from RP.
[HSD-ES] 2103617549 : [BMP] When set clear CMOS jumper 2 times continuous, at the 2nd time no 5220 error log at Error managerˇ±.
[HSD-ES] 1504517035 : [AEP WFP] No PXE / HTTP boot device in BIOS boot menu with debug version BIOS.
[HSD-ES] 2006647270 : BKC AEP - Intel NVM DIMM showing 'Not Installed' on Memory Configuration, on a platform with AEP DIMMs.
[HSD-ES]2006655955 [BMP] NIC Configuration is blank on BMP BIOS setup. BMP doesn't support onboard network devices.
[HSD-ES] 2103617864 : [WFP] BIOS will not keep boot order after remove boot device.
[HSD-ES] 2103617695  [BMP] SMBIOS Type 9 is incorrect about bus/dev/fun number and ˇ°Current Usageˇ±.
[HSD-ES] 2103618002 : [BMP] SMBIOS Type 17 will report MBIST fail DIMM but the DIMM size is 0x0000.
[HSD-ES] 1504530742  [AEP WFP]Lock NGN CSRs is hidden option in BIOS setup on BIOS 563.
Reference code version: 20170724_CP_PURLEY_510_D02.
================================================================================
                               01.00.0578
================================================================================
[HSD-ES] 1504539640 : [PC Stitching] Sync Microcode 0x26 from RP.
[HSD-ES] 2103617705 : The system SATA HDDs will Warning on BMC web.
[HSD-ES] 1504536397 : [BNP,STP,WFP]Syscfg_V14.1.16: The boot order is different between press F9 and key command ˇ°syscfg /bldfs ˇ° ˇ± "to load default on Legacy mode.
[HSD-ES] 2103618058 : [BMP] Login to BIOS with User Password, UEFI option ROM control setting still available.
[HSD-ES] 1504538762 : [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1894 from RP.
[HSD-ES] 220236632 : SDP:  BIOS menu does not have option to configure and update AEP DIMM.
[HSD-ES] 2006649895 : FRB2 Asserted during system boot when 7 QLogic PCI cards are inserted on the system.
[HSD-ES] 2006650537 : [S2600BP]DMI Information for the network device is not correct. "enp" as oppose to "eno".
[HSD-ES] 2103617966 : [WFP] The warning message is incorrect when set Admin/User PWD the same.
Reference code version: 20170718_CP_PURLEY_509_D11.
================================================================================
                               01.00.0570
================================================================================
[HSD-ES] 1504533006 : [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1892 from RP.
[HSD-ES] 1504411203 : CCB#1751[Purley BIOS]Need to port McAfee work from Grantley BIOS to Purley BIOS for McAfee on STP.
[HSD-ES] 1504403422 : Update ME FW to the new version.
[HSD-ES] 1504531663 : [PC Stitching] Sync Microcode 0x26 for SKX H0 from RP.
[HSD-ES] 220198494 : SDP: System beep during the warm reset, hang or restart itself after beep.
5221152: [Bakerville_SKXD]Linux boot will hang after enabling Linux Log manually.
[HSD-ES] 1504528902 : [PC Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1890 from RP.
[HSD-ES] 1504521041 : [BMP]Syscfg_V14_1:Command:syscfg /bldfs  "" and F9 load different Bios default Boot Order.
[HSD-ES] 1504527306 : Integration BIOS ACM & SINIT to 1.3.2.
[HSD-ES] 1604381641 : [AEP WFP] Can't update ME version with Debug BIOS.
[HSD-ES] 2006650537 : [S2600BP]DMI Information for the network device is not correct. "enp" as oppose to "eno".
Reference code version: 20170711_CP_PURLEY_508_D41.
================================================================================
                               01.00.0563
================================================================================
[HSD-ES] 1504525966 : [PC Stitching]Sync Intel Apache Pass UEFI driver 01.00.00.1885 from RP.
[HSD-ES] 220203024 : 3 slot riser + 4P/8P switch + VROC key + VMD enabled does not enable VROC OpROM in some cases.
[HSD-ES] 1504403422 : Update ME FW to the new version.
[HSD-ES] 2103617718 : [BNP] Windows OS eventview not report whea eventID 23 after SBE is sucessfully injected with BIOS X0008.
[HSD-ES] 2103617732 : [BNP] SFP+ SKU socket0 1a,1c always show x8 whatever CPU1 IOU1 setting.
Reference code version: 20170629_CP_PURLEY_1006_D26.
================================================================================
                               01.00.0552
================================================================================
[HSD-ES] 1604389382 [PC-Stitching] Sync Intel Apache Pass UEFI driver 01.00.00.1881 from RP.
[HSD-ES] 1504437936 SDLS4]REACT-2017-1-OpenSSL upgrade for security vulnerability.
[HSD-ES] 2103617693 : [BNP]UUT cannot boot to EFI Shell automatically in recovery mode.
[HSD-ES] 2103617198 : [BNP]Can not build raid if pcie ssd connect VMD Port CPU1 1C/1D & VMD Port CPU2 3A/3B.
[HSD-ES] 2103617682 : [BNP]Riser_Slot_X Bifurcation's help text is incorrect in BIOS X0007 and BIOS Setup Degin v1.04.
[HSD-ES] 1504521158 : Optimize slot3 VMD option display.
[HSD-ES] 1504452197 : #CCB 1900 [WFP BIOS] Enable Symmetric QAT Support in BIOS for hardware CCB 1893.
[HSD-ES] 1504521139 : WFP and BMP short team solution for 10Gbe MAC address need BIOS sent it to BMC FW.
[HSD-ES] 1504520668 : GPIO need to be locked on all of platform.
[HSD-ES] 1504451515 : The VMD port name in Volume Management Device is not same to circuit diagram.
[HSD-ES 1504437936 : [SDLS4]REACT-2017-1-OpenSSL upgrade for security vulnerability.
Reference code version: 20170622_CP_PURLEY_1006_D11.
================================================================================
                               01.00.0542
================================================================================
[HSD-ES] 1504518908  [PC-Stitching] Sync microcode patch 0x22 from RP.
[HSD-ES] 1604381670  [HSD-ES] Add SFID support for Wolfpass CR projects.
[HSD-ES] 1504508518  [AEP WFP] System will hang up during warm reset.
[HSD-ES] 2103617416  [WFP] Pause key will not suspend the FRB2 timer during post process, thus system will reboot after 6 min.
[HSD-ES] 1504515553  Integration BIOS ACM to 1.3.1.
[HSD-ES] 1504513466  [AEP WFP] AEP DIMM memory error injection feature malfunction.
[HSD-ES] 1604379415   [PC Stitching]Request to Add Auto-generated IFWI Ingredient table for WolfPass CR project.
[HSD-ES] 1504452197  #CCB 1900 [WFP BIOS] Enable Symmetric QAT Support in BIOS for hardware CCB 1893.
[HSD-ES] 2103615650  [Cert] HLK USB 3.0 Exposed Port System Test will be fail.
[HSD-ES] 1504515646  [PC Stitching] Sync WFT-S NVM v3.38 to CR project.
Reference code version: 20170613_CP_PURLEY_1005_D05.
================================================================================
                               01.00.0536
================================================================================
[HSD-ES] 2103616570 [WFP]SUT can not boot to Win2016 with FAB2 Switch card.
[HSD-ES] 1504513467 [PC Stitching] Sync Microcode 0x22 for SKX H0 from RP.
[HSD-ES]1504514934 [PC-Stitching] Sync Apache Pass UEFI driver 01.00.00.1871 from RP.
Reference code version:  20170608_CP_PURLEY_1004_D07.
================================================================================
                               01.00.0534
================================================================================
501829 - [HSD-ES] 2103617249 SUT halt at 0x32 during POST with B0 stepping CPU.
501832 -[HSD-ES]2103617276: [STP] The first digit of BMC build number in "BIOS post information" isn't printed if it's 0.
501851 -[HSD-ES]2103617250 PCIe SSD cann't be detected by Redhat 7.3 on 6Port 3408 or 6Port 3008 after plug out/in. 
502152 -[HSD-ES]1504403422: Update ME SPS version to PV MR 206.
502156 -[HSD-ES] 2103616705: - OEM Table ID is incorrect in ACPI table.
502543 -[HSD-ES]2103616570 :SUT can not boot to Win2016 with FAB2 Switch card. 
502653 -[HSD-ES] 1504511152 [AEP WFP] resolve CR release mode build failure.
503050 -[HSD-ES] 1504511969 Integrate the NVMDIMMDriver/NVMDIMMHii v01.00.00.1869 from RP.
503097 -[HSD-ES]220167803: Blue Mountain Pass BIOS needs load the Retime EQ Parameters.
503569 -[HSD-ES]1504514934[PC-Stitching] Sync Apache Pass UEFI driver 01.00.00.1871 from RP.
================================================================================
                               01.00.0530
================================================================================
1. 5346223: Integrate Intel Apache Pass UEFI driver 01.00.00.1869.
